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型號(hào)：	S80C32XXX-40R
廠商：	TEMIC SEMICONDUCTORS
元件分類：	微控制器/微處理器
英文描述：	8-BIT, 40 MHz, MICROCONTROLLER, PQCC44
文件頁(yè)數(shù)：	792/1021頁(yè)
文件大?。?/td>	15196K
代理商：	S80C32XXX-40R

32072H–AVR32–10/2012

AT32UC3A3

Power Management

In sleep mode, the ADC clock is automatically stopped after each conversion. As the logic is

small and the ADC cell can be put into sleep mode, the Power Manager has no effect on the

ADC behavior.

The clock for the ADC bus interface (CLK_ADC) is generated by the Power Manager. This clock

is enabled at reset, and can be disabled in the Power Manager. It is recommended to disable the

ADC before disabling the clock, to avoid freezing the ADC in an undefined state.

The CLK_ADC clock frequency must be in line with the ADC characteritics. Refer to Electrical

Characteristics section for details.

Interrupts

The ADC interrupt request line is connected to the interrupt controller. Using the ADC interrupt

requires the interrupt controller to be programmed first.

Analog Inputs

The analog input pins can be multiplexed with I/O lines. In this case, the assignment of the ADC

input is automatically done as soon as the corresponding I/O is configured through the I/O con-

toller. By default, after reset, the I/O line is configured as a logic input.

Timer Triggers

Timer Counters may or may not be used as hardware triggers depending on user requirements.

Thus, some or all of the timer counters may be non-connected.

Functional Description

Analog-to-digital Conversion

The ADC uses the ADC Clock to perform conversions. Converting a single analog value to a 10-

bit digital data requires sample and hold clock cycles as defined in the Sample and Hold Time

field of the Mode Register (MR.SHTIM) and 10 ADC Clock cycles. The ADC Clock frequency is

selected in the Prescaler Rate Selection field of the MR register (MR.PRESCAL).

The ADC Clock range is between CLK_ADC/2, if the PRESCAL field is 0, and CLK_ADC/128, if

the PRESCAL field is 63 (0x3F). The PRESCAL field must be written in order to provide an ADC

Clock frequency according to the parameters given in the Electrical Characteristics chapter.

Conversion Reference

The conversion is performed on a full range between 0V and the reference voltage connected to

VDDANA. Analog input values between these voltages are converted to digital values based on

a linear conversion.

Conversion Resolution

The ADC supports 8-bit or 10-bit resolutions. The 8-bit selection is performed by writing a one to

the Resolution bit in the MR register (MR.LOWRES). By default, after a reset, the resolution is

the highest and the Converted Data field in the Channel Data Registers (CDRn.DATA) is fully

used. By writing a one to the LOWRES bit, the ADC switches in the lowest resolution and the

conversion results can be read in the eight lowest significant bits of the Channel Data Registers

(CDRn). The two highest bits of the DATA field in the corresponding CDRn register will be read

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