349
32072H–AVR32–10/2012
AT32UC3A3
0x158
Channel 3Destination Scatter Register
DSR3
Read/Write
0x00000000
0x2C0
Raw Status for IntTfr Interrupt
RawTfr
Read-only
0x00000000
0x2C8
Raw Status for IntBlock Interrupt
RawBlock
Read-only
0x00000000
0x2D0
Raw Status for IntSrcTran Interrupt
RawSrcTran
Read-only
0x00000000
0x2D8
Raw Status for IntDstTran Interrupt
RawDstTran
Read-only
0x00000000
0x2E0
Raw Status for IntErr Interrupt
RawErr
Read-only
0x00000000
0x2E8
Status for IntTfr Interrupt
StatusTfr
Read-only
0x00000000
0x2F0
Status for IntBlock Interrupt
StatusBlock
Read-only
0x00000000
0x2F8
Status for IntSrcTran Interrupt
StatusSrcTran
Read-only
0x00000000
0x300
Status for IntDstTran Interrupt
StatusDstTran
Read-only
0x00000000
0x308
Status for IntErr Interrupt
StatusErr
Read-only
0x00000000
0x310
Mask for IntTfr Interrupt
MaskTfr
Read/Write
0x00000000
0x318
Mask for IntBlock Interrupt
MaskBlock
Read/Write
0x00000000
0x320
Mask for IntSrcTran Interrupt
MaskSrcTran
Read/Write
0x00000000
0x328
Mask for IntDstTran Interrupt
MaskDstTran
Read/Write
0x00000000
0x330
Mask for IntErr Interrupt
MaskErr
Read/Write
0x00000000
0x338
Clear for IntTfr Interrupt
ClearTfr
Write-only
0x00000000
0x340
Clear for IntBlock Interrupt
ClearBlock
Write-only
0x00000000
0x348
Clear for IntSrcTran Interrupt
ClearSrcTran
Write-only
0x00000000
0x350
Clear for IntDstTran Interrupt
ClearDstTran
Write-only
0x00000000
0x358
Clear for IntErr Interrupt
ClearErr
Write-only
0x00000000
0x360
Status for each interrupt type
StatusInt
Read-only
0x00000000
0x368
Source Software Transaction Request Register
ReqSrcReg
Read/Write
0x00000000
0x370
Destination Software Transaction Request Register
ReqDstReg
Read/Write
0x00000000
0x378
Single Source Transaction Request Register
SglReqSrcReg
Read/Write
0x00000000
0x380
Single Destination Transaction Request Register
SglReqDstReg
Read/Write
0x00000000
0x388
Last Source Transaction Request Register
LstSrcReg
Read/Write
0x00000000
0x390
Last Destination Transaction Request Register
LstDstReg
Read/Write
0x00000000
0x398
DMA Configuration Register
DmaCfgReg
Read/Write
0x00000000
0x3A0
DMA Channel Enable Register
ChEnReg
Read/Write
0x00000000
0x3F8
DMA Component ID Register Low
DmaCompIdRegL
Read-only
0x44571110
0x3FC
DMA Component ID Register High
DmaCompIdRegH
Read-only
0x3230362A
Table 19-2.
DMA Controller Memory Map (Continued)
Offset
Register
Register Name
Access
Reset Value