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型號(hào)：	S80C32XXX-40R
廠商：	TEMIC SEMICONDUCTORS
元件分類(lèi)：	微控制器/微處理器
英文描述：	8-BIT, 40 MHz, MICROCONTROLLER, PQCC44
文件頁(yè)數(shù)：	844/1021頁(yè)
文件大?。?/td>	15196K
代理商：	S80C32XXX-40R

32072H–AVR32–10/2012

AT32UC3A3

CMDR register (CMDR.SPCMD) must be set to three to issue the CE-ATA completion Signal

Disable Command.

CE-ATA Error Recovery

Several methods of ATA command failure may occur, including:

No response to an MMC command, such as RW_MULTIPLE_REGISTER (CMD60).

CRC is invalid for an MMC command or response.

CRC16 is invalid for an MMC data packet.

ATA Status register reflects an error by setting the ERR bit to one.

The command completion signal does not arrive within a host specified time out period.

Error conditions are expected to happen infrequently. Thus, a robust error recovery mechanism

may be used for each error event. The recommended error recovery procedure after a time-out

Issue the command completion signal disable if IEN was cleared to zero and the

RW_MULTIPLE_BLOCK (CMD61) response has been received.

Issue STOP_TRANSMISSION (CMD12) and successfully receive the R1 response.

Issue a software reset to the CE-ATA device using FAST_IO (CMD39).

If STOP_TRANMISSION (CMD12) is successful, then the device is again ready for ATA com-

mands. However, if the error recovery procedure does not work as expected or there is another

time-out, the next step is to issue GO_IDLE_STATE (CMD0) to the device. GO_IDLE_STATE

(CMD0) is a hard reset to the device and completely resets all device states.

Note that after issuing GO_IDLE_STATE (CMD0), all device initialization needs to be completed

again. If the CE-ATA device completes all MMC commands correctly but fails the ATA command

with the ERR bit set in the ATA Status register, no error recovery action is required. The ATA

command itself failed implying that the device could not complete the action requested, how-

ever, there was no communication or protocol failure. After the device signals an error by setting

the ERR bit to one in the ATA Status register, the host may attempt to retry the command.

MCI Boot Operation Mode

In boot operation mode, the processor can read boot data from the slave (MMC device) by keep-

ing the CMD line low after power-on before issuing CMD1. The data can be read from either

boot area or user area depending on register setting.

Boot Procedure, processor mode

Configure MCI2 data bus width programming SDCBUS Field in the MCI_SDCR regis-

ter. The BOOT_BUS_WIDTH field located in the device Extended CSD register must

be set accordingly.

Set the bytecount to 512 bytes and the blockcount to the desired number of block, writ-

ing BLKLEN and BCNT fields of the MCI_BLKR Register.

Issue the Boot Operation Request command by writing to the MCI_CMDR register with

SPCMD field set to BOOTREQ, TRDIR set to READ and TRCMD set to “start data

The BOOT_ACK field located in the MCI_CMDR register must be set to one, if the

BOOT_ACK field of the MMC device located in the Extended CSD register is set to one.

Host processor can copy boot data sequentialy as soon as the RXRDY flag is asserted.

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