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參數(shù)資料
| 型號(hào)： | S80C32-44:RD |
| 廠商： | ATMEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, 44 MHz, MICROCONTROLLER, PQCC44 |
| 封裝： | PLASTIC, LCC-44 |
| 文件頁(yè)數(shù)： | 23/152頁(yè) |
| 文件大?。?/td> | 2528K |
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119
2486AA–AVR–02/2013
ATmega8(L)
During asynchronous operation, the synchronization of the Interrupt Flags for the
asynchronous timer takes three processor cycles plus one timer cycle. The timer is therefore
advanced by at least one before the processor can read the timer value causing the setting
of the Interrupt Flag. The Output Compare Pin is changed on the timer clock and is not
synchronized to the processor clock
Timer/Counter
Interrupt Mask
Register – TIMSK
Bit 7 – OCIE2: Timer/Counter2 Output Compare Match Interrupt Enable
When the OCIE2 bit is written to one and the I-bit in the Status Register is set (one), the
Timer/Counter2 Compare Match interrupt is enabled. The corresponding interrupt is executed if
a Compare Match in Timer/Counter2 occurs (that is, when the OCF2 bit is set in the
Timer/Counter Interrupt Flag Register – TIFR).
Bit 6 – TOIE2: Timer/Counter2 Overflow Interrupt Enable
When the TOIE2 bit is written to one and the I-bit in the Status Register is set (one), the
Timer/Counter2 Overflow interrupt is enabled. The corresponding interrupt is executed if an
overflow in Timer/Counter2 occurs (that is, when the TOV2 bit is set in the Timer/Counter Inter-
rupt Flag Register – TIFR).
Timer/Counter
Interrupt Flag Register
– TIFR
Bit 7 – OCF2: Output Compare Flag 2
The OCF2 bit is set (one) when a Compare Match occurs between the Timer/Counter2 and the
data in OCR2 – Output Compare Register2. OCF2 is cleared by hardware when executing the
corresponding interrupt Handling Vector. Alternatively, OCF2 is cleared by writing a logic one to
the flag. When the I-bit in SREG, OCIE2 (Timer/Counter2 Compare Match Interrupt Enable), and
OCF2 are set (one), the Timer/Counter2 Compare Match Interrupt is executed.
Bit 6 – TOV2: Timer/Counter2 Overflow Flag
The TOV2 bit is set (one) when an overflow occurs in Timer/Counter2. TOV2 is cleared by hard-
ware when executing the corresponding interrupt Handling Vector. Alternatively, TOV2 is
cleared by writing a logic one to the flag. When the SREG I-bit, TOIE2 (Timer/Counter2 Overflow
Interrupt Enable), and TOV2 are set (one), the Timer/Counter2 Overflow interrupt is executed. In
PWM mode, this bit is set when Timer/Counter2 changes counting direction at 0x00.
Bit
765
4321
0
OCIE2
TOIE2
TICIE1
OCIE1A
OCIE1B
TOIE1
–
TOIE0
TIMSK
Read/Write
R/W
R
R/W
Initial Value
000
0000
0
Bit
765
4321
0
OCF2
TOV2
ICF1
OCF1A
OCF1B
TOV1
–
TOV0
TIFR
Read/Write
R/W
R
R/W
Initial Value
000
0000
0
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