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2486AA–AVR–02/2013
ATmega8(L)
Table 45 shows the COM21:0 bit functionality when the WGM21:0 bits are set to phase correct
PWM mode.
Note:
1. A special case occurs when OCR2 equals TOP and COM21 is set. In this case, the Compare
Bit 2:0 – CS22:0: Clock Select
The three clock select bits select the clock source to be used by the Timer/Counter, see
TableTimer/Counter
Register – TCNT2
The Timer/Counter Register gives direct access, both for read and write operations, to the
Timer/Counter unit 8-bit counter. Writing to the TCNT2 Register blocks (removes) the Compare
Match on the following timer clock. Modifying the counter (TCNT2) while the counter is running,
introduces a risk of missing a Compare Match between TCNT2 and the OCR2 Register.
Output Compare
Register – OCR2
The Output Compare Register contains an 8-bit value that is continuously compared with the
counter value (TCNT2). A match can be used to generate an Output Compare interrupt, or to
generate a waveform output on the OC2 pin.
Table 45. Compare Output Mode, Phase Correct PWM Mode
COM21
COM20
Description
0
Normal port operation, OC2 disconnected
01
Reserved
10
Clear OC2 on Compare Match when up-counting. Set OC2 on Compare
Match when downcounting
11
Set OC2 on Compare Match when up-counting. Clear OC2 on Compare
Match when downcounting
Table 46. Clock Select Bit Description
CS22
CS21
CS20
Description
0
No clock source (Timer/Counter stopped)
00
1
clkT2S/(No prescaling)
01
0
clkT2S/8 (From prescaler)
01
1
clkT2S/32 (From prescaler)
10
0
clkT2S/64 (From prescaler)
10
1
clkT2S/128 (From prescaler)
11
0
clk
T
2S/256 (From prescaler)
11
1
clkT2S/1024 (From prescaler)
Bit
765
4321
0
TCNT2[7:0]
TCNT2
Read/Write
R/W
Initial Value
000
0000
0
Bit
765
4321
0
OCR2[7:0]
OCR2
Read/Write
R/W
Initial Value
000
0000
0