892
32072H–AVR32–10/2012
AT32UC3A3
These sizes are selected by writing the Cipher Feedback Data Size field in the MR register
(MR.CFDS).
33.4.2
Start Modes
The Start Mode field in the MR register (MR.SMOD) allows selection of the encryption (or
decryption) start mode.
33.4.2.1
Manual mode
The sequence is as follows:
Write the 128-bit/192-bit/256-bit key in the KEYWnR registers.
Write the initialization vector (or counter) in the IVnR registers.
Note:
The Initialization Vector Registers concern all modes except ECB.
Write the Data Ready bit in the Interrupt Enable Register (IER.DATRDY), depending on
whether an interrupt is required or not at the end of processing.
Write the data to be encrypted/decrypted in the authorized Input Data Registers (IDATAnR).
Note:
In 64-bit CFB mode, writing to IDATA3R and IDATA4R registers is not allowed and may lead to
errors in processing.
Note:
In 32-bit, 16-bit and 8-bit CFB modes, writing to IDATA2R, IDATA3R and IDATA4R registers is not
allowed and may lead to errors in processing.
Write the START bit in the Control Register (CR.START) to begin the encryption or the
decryption process.
When the processing completes, the DATRDY bit in the Interrupt Status Register
(ISR.DATRDY) is set.
If an interrupt has been enabled by writing the IER.DATRDY bit, the interrupt line of the AES
is activated.
When the software reads one of the Output Data Registers (ODATAxR), the ISR.DATRDY bit
is cleared.
33.4.2.2
Automatic mode
The automatic mode is similar to the manual one, except that in this mode, as soon as the cor-
rect number of IDATAnR Registers is written, processing is automatically started without any
action in the CR register.
Table 33-1.
Authorized Input Data Registers
Operation Mode
IDATAnR to Write
ECB
All
CBC
All
OFB
All
128-bit CFB
All
64-bit CFB
IDATA1R and IDATA2R
32-bit CFB
IDATA1R
16-bit CFB
IDATA1R
8-bit CFB
IDATA1R
CTR
All