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您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄25635 > S80C32-40SHXXX:RD (TEMIC SEMICONDUCTORS) 8-BIT, 40 MHz, MICROCONTROLLER, PQCC44 PDF資料下載

型號(hào)：	S80C32-40SHXXX:RD
廠商：	TEMIC SEMICONDUCTORS
元件分類：	微控制器/微處理器
英文描述：	8-BIT, 40 MHz, MICROCONTROLLER, PQCC44
文件頁(yè)數(shù)：	4/1021頁(yè)
文件大?。?/td>	15196K

32072H–AVR32–10/2012

AT32UC3A3

Sleep Mode activation needs additional A to D conversion

If the ADC sleep mode is activated when the ADC is idle the ADC will not enter sleep mode

before after the next AD conversion.

Fix/Workaround

Activate the sleep mode in the mode register and then perform an AD conversion.

ISO7816 info register US_NER cannot be read

The NER register always returns zero.

Fix/Workaround

The LIN ID is not transmitted in mode PDCM='0'

Fix/Workaround

Using USART in mode LIN master with the PDCM bit = '0', the LINID written at the first

address of the transmit buffer is not used. The LINID must be written in the LINIR register,

after the configuration and start of the PDCA transfer. Writing the LINID in the LINIR register

will start the transfer whenever the PDCA transfer is ready.

The LINID interrupt is only available for the header reception and not available for the

header transmission

Fix/Workaround

USART LIN mode is not functional with the PDCA if PDCM bit in LINMR register is set

If a PDCA transfer is initiated in USART LIN mode with PDCM bit set to 1, the transfer never

Fix/Workaround

Only use PDCM=0 configuration with the PDCA transfer.

The RTS output does not function correctly in hardware handshaking mode

The RTS signal is not generated properly when the USART receives data in hardware hand-

shaking mode. When the Peripheral DMA receive buffer becomes full, the RTS output

should go high, but it will stay low.

Fix/Workaround

Do not use the hardware handshaking mode of the USART. If it is necessary to drive the

RTS output high when the Peripheral DMA receive buffer becomes full, use the normal

mode of the USART. Configure the Peripheral DMA Controller to signal an interrupt when

the receive buffer is full. In the interrupt handler code, write a one to the RTSDIS bit in the

USART Control Register (CR). This will drive the RTS output high. After the next DMA trans-

fer is started and a receive buffer is available, write a one to the RTSEN bit in the USART

CR so that RTS will be driven low.

ISO7816 Mode T1: RX impossible after any TX

RX impossible after any TX.

Fix/Workaround

SOFT_RESET on RX+ Config US_MR + Config_US_CR.

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相關(guān)代理商/技術(shù)參數(shù)	參數(shù)描述
S80C32-42	制造商:未知廠家制造商全稱:未知廠家功能描述:8-Bit Microcontroller
S80C32-42R	制造商:未知廠家制造商全稱:未知廠家功能描述:8-Bit Microcontroller
S80C32-44	制造商:未知廠家制造商全稱:未知廠家功能描述:8-Bit Microcontroller
S80C32-44R	制造商:未知廠家制造商全稱:未知廠家功能描述:8-Bit Microcontroller
S80C32-L16	制造商:未知廠家制造商全稱:未知廠家功能描述:8-Bit Microcontroller

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