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型號(hào)：	S80C32-40SHXXX:RD
廠商：	TEMIC SEMICONDUCTORS
元件分類：	微控制器/微處理器
英文描述：	8-BIT, 40 MHz, MICROCONTROLLER, PQCC44
文件頁(yè)數(shù)：	618/1021頁(yè)
文件大?。?/td>	15196K

32072H–AVR32–10/2012

AT32UC3A3

To free its memory, the user shall write a zero to the UECFGn.ALLOC bit. The n+ 1 pipe/end-

point memory window then slides down and its data is lost. Note that the following pipe/endpoint

memory windows (from n+2) does not slide.

Figure 27-7 on page 635 illustrates the allocation and reorganization of the DPRAM in a typical

Figure 27-7. Allocation and Reorganization of the DPRAM

The pipes/endpoints 0 to 5 are enabled, configured and allocated in ascending order.

Each pipe/endpoint then owns a memory area in the DPRAM.

The pipe/endpoint 3 is disabled, but its memory is kept allocated by the controller.

In order to free its memory, its ALLOC bit is written to zero. The pipe/endpoint 4 mem-

ory window slides down, but the pipe/endpoint 5 does not move.

If the user chooses to reconfigure the pipe/endpoint 3 with a larger size, the controller

allocates a memory area after the pipe/endpoint 2 memory area and automatically

slides up the pipe/endpoint 4 memory window. The pipe/endpoint 5 does not move and

a memory conflict appears as the memory windows of the pipes/endpoints 4 and 5

overlap. The data of these pipes/endpoints is potentially lost.

There is no way the data of the pipe/endpoint 0 can be lost (except if it is de-allocated) as

memory allocation and de-allocation may affect only higher pipes/endpoints.

Deactivating then reactivating a same pipe/endpoint with the same configuration only

modifies temporarily the controller DPRAM pointer and size for this pipe/endpoint, but

nothing changes in the DPRAM, so higher endpoints seem to not have been moved and their

data is preserved as far as nothing has been written or received into them while changing the

allocation state of the first pipe/endpoint.

When the user write a one to the ALLOC bit, the Configuration OK Status bit in the Endpoint

n Status register (UESTAn.CFGOK) is set only if the configured size and number of banks

are correct compared to their maximal allowed values for the endpoint and to the maximal

U(P/E)RST.(E)PENn = 1

U(P/E)CFGn.ALLOC = 1

Pipe/Endpoint 3

Pipe/Endpoint 3

Memory Freed

PEP3 (larger size)

Pipe/Endpoint 3

PEP4 Lost Memory

U(P/E)RST.(E)PEN3 = 0

(ALLOC stays at 1)

U(P/E)CFG3.ALLOC = 0

U(P/E)RST.(E)PEN3 = 1

U(P/E)CFG3.ALLOC = 1

Pipes/Endpoints 0..5

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相關(guān)代理商/技術(shù)參數(shù)	參數(shù)描述
S80C32-42	制造商:未知廠家制造商全稱:未知廠家功能描述:8-Bit Microcontroller
S80C32-42R	制造商:未知廠家制造商全稱:未知廠家功能描述:8-Bit Microcontroller
S80C32-44	制造商:未知廠家制造商全稱:未知廠家功能描述:8-Bit Microcontroller
S80C32-44R	制造商:未知廠家制造商全稱:未知廠家功能描述:8-Bit Microcontroller
S80C32-L16	制造商:未知廠家制造商全稱:未知廠家功能描述:8-Bit Microcontroller

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