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型號：	S80C32-40SHXXX:RD
廠商：	TEMIC SEMICONDUCTORS
元件分類：	微控制器/微處理器
英文描述：	8-BIT, 40 MHz, MICROCONTROLLER, PQCC44
文件頁數(shù)：	388/1021頁
文件大小：	15196K

32072H–AVR32–10/2012

AT32UC3A3

BITS: Bits Per Transfer

The BITS field determines the number of data bits transferred. Reserved values should not be used.

CSAAT: Chip Select Active After Transfer

1: The Peripheral Chip Select does not rise after the last transfer is achieved. It remains active until a new transfer is requested

on a different chip select.

0: The Peripheral Chip Select Line rises as soon as the last transfer is achieved.

CSNAAT: Chip Select Not Active After Transfer (Ignored if CSAAT = 1)

0: The Peripheral Chip Select does not rise between two transfers if the TDR is reloaded before the end of the first transfer and

if the two transfers occur on the same Chip Select.

1: The Peripheral Chip Select rises systematically between each transfer performed on the same slave for a minimal duration of:

(if DLYBCT field is different from 0)

(if DLYBCT field equals 0)

NCPHA: Clock Phase

1: Data is captured after the leading (inactive-to-active) edge of SPCK and changed on the trailing (active-to-inactive) edge of

0: Data is changed on the leading (inactive-to-active) edge of SPCK and captured after the trailing (active-to-inactive) edge of

NCPHA determines which edge of SPCK causes data to change and which edge causes data to be captured. NCPHA is used

with CPOL to produce the required clock/data relationship between master and slave devices.

CPOL: Clock Polarity

1: The inactive state value of SPCK is logic level one.

0: The inactive state value of SPCK is logic level zero.

Bits Per Transfer

-----------------------

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相關(guān)代理商/技術(shù)參數(shù)	參數(shù)描述
S80C32-42	制造商:未知廠家制造商全稱:未知廠家功能描述:8-Bit Microcontroller
S80C32-42R	制造商:未知廠家制造商全稱:未知廠家功能描述:8-Bit Microcontroller
S80C32-44	制造商:未知廠家制造商全稱:未知廠家功能描述:8-Bit Microcontroller
S80C32-44R	制造商:未知廠家制造商全稱:未知廠家功能描述:8-Bit Microcontroller
S80C32-L16	制造商:未知廠家制造商全稱:未知廠家功能描述:8-Bit Microcontroller

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