參數(shù)資料
型號： S71WS512N80BFEZZ3
廠商： Spansion Inc.
英文描述： Stacked Multi-Chip Product (MCP) Flash Memory and pSRAM CMOS 1.8 Volt
中文描述： 堆疊式多芯片產(chǎn)品（MCP）的閃存和移動存儲芯片的CMOS 1.8伏特
文件頁數(shù)： 98/142頁
文件大?。?/td> 1996K
代理商： S71WS512N80BFEZZ3
98
128Mb pSRAM
S71WS512NE0BFWZZ_00_A1 June 28, 2004
P r e l i m i n a r y
FUNCTIONAL DESCRIPTION
This device supports asynchronous page read & normal write operation and syn-
chronous burst read & burst write operation for faster memory access and
features three kinds of power down modes for power saving as user configuable
option.
Power-up
It is required to follow the power-up timing to start executing proper device
operation. Refer to POWER-UP Timing. After Power-up, the device defaults to
asynchronous page read & normal write operation mode with sleep power down
feature.
Configuration Register
The Configuration Register (CR) is used to configure the type of device function
among optional features. Each selection of features is set through CR Set sequence
after Power-up. If CR Set sequence is not performed after power-up, the device
is configured for asynchronous operation with sleep power down feature as default
configuration
CR Set Sequence
The CR Set requires total 6 read/write operation with unique address. Between
each read/write operation requires that device being in standby mode. Following
table shows the detail sequence.
The first cycle is to read from most significant address (MSB).
The second and third cycle are to write back the data (RDa) read by first cycle.
If the second or third cycle is written into the different address, the CR Set is
cancelled and the data written by the second or third cycle is valid as a normal
write operation.
The forth and fifth cycle is to write to MSB. The data of forth and fifth cycle is
don’t-care. If the forth or fifth cycle is written into different address, the CR Set
is also cancelled but write data may not be written as normal write operation.
The last cycle is to read from specific address key for mode selection. And read
data (RDb) is invalid.
Once this CR Set sequence is performed from an initial CR set to the other new
CR set, the written data stored in memory cell array may be lost. So, it should
perform the CR Set sequence prior to regular read/write operation if necessary
to change from default configuration.
Cycle #
Operation
Address
Data
1st
Read
7FFFFFh (MSB)
Read Data (RDa)
2nd
Write
7FFFFFh
RDa
3rd
Write
7FFFFFh
RDa
4th
Write
7FFFFFh
X
5th
Write
7FFFFFh
X
6th
Read
Address Key
Read Data (RDb)
相關(guān)PDF資料
PDF描述
S71WS512N80BFIZZ0 Stacked Multi-Chip Product (MCP) Flash Memory and pSRAM CMOS 1.8 Volt
S71WS512N80BFIZZ2 Stacked Multi-Chip Product (MCP) Flash Memory and pSRAM CMOS 1.8 Volt
S71WS512N80BFIZZ3 Stacked Multi-Chip Product (MCP) Flash Memory and pSRAM CMOS 1.8 Volt
S71WS512N80BFWZZ0 Stacked Multi-Chip Product (MCP) Flash Memory and pSRAM CMOS 1.8 Volt
S71WS512N80BFWZZ2 Stacked Multi-Chip Product (MCP) Flash Memory and pSRAM CMOS 1.8 Volt
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
S71WS512N80BFIZZ0 制造商:SPANSION 制造商全稱:SPANSION 功能描述:Stacked Multi-Chip Product (MCP) Flash Memory and pSRAM CMOS 1.8 Volt
S71WS512N80BFIZZ2 制造商:SPANSION 制造商全稱:SPANSION 功能描述:Stacked Multi-Chip Product (MCP) Flash Memory and pSRAM CMOS 1.8 Volt
S71WS512N80BFIZZ3 制造商:SPANSION 制造商全稱:SPANSION 功能描述:Stacked Multi-Chip Product (MCP) Flash Memory and pSRAM CMOS 1.8 Volt
S71WS512N80BFWZZ0 制造商:SPANSION 制造商全稱:SPANSION 功能描述:Stacked Multi-Chip Product (MCP) Flash Memory and pSRAM CMOS 1.8 Volt
S71WS512N80BFWZZ2 制造商:SPANSION 制造商全稱:SPANSION 功能描述:Stacked Multi-Chip Product (MCP) Flash Memory and pSRAM CMOS 1.8 Volt
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