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參數(shù)資料
| 型號(hào)： | S71WS512N80BFEZZ3 |
| 廠商： | Spansion Inc. |
| 英文描述： | Stacked Multi-Chip Product (MCP) Flash Memory and pSRAM CMOS 1.8 Volt |
| 中文描述： | 堆疊式多芯片產(chǎn)品（MCP）的閃存和移動(dòng)存儲(chǔ)芯片的CMOS 1.8伏特 |
| 文件頁(yè)數(shù)： | 111/142頁(yè) |
| 文件大?。?/td> | 1996K |
| 代理商： | S71WS512N80BFEZZ3 |
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June 28, 2004 S71WS512NE0BFWZZ_00_A1
128Mb pSRAM
111
P r e l i m i n a r y
AC CHARACTERISTICS (Continued)
ASYNCHRONOUS WRITE OPERATION
Notes
*1: Maximum value is applicable if CE#1 is kept at Low without any address change. If the relaxation is needed
by system operation, please contact local FUJITSU representative for the relaxation of 1ms limitation.
*2: Minimum value must be equal or greater than the sum of write pulse (t
CW
, t
WP
or t
BW
) and write recovery
time (t
WRC
, t
WR
or t
BR
).
*3: Write pulse is defined from High to Low transition of CE#1, WE# or LB# / UB#, whichever occurs last.
*4: t
VPL
is specified from the negative edge of either CE#1 or ADV# whichever comes late.
*5: Write recovery is defined from Low to High transition of CE#1, WE# or LB# / UB#, whichever occurs first.
*6: If OE# is Low after minimum t
OHCL
, read cycle is initiated. In other word, OE# must be brought to High
within 5ns after CE#1 is brought to Low. Once read cycle is initiated, new write pulse should be input after
minimum t
RC
is met.
*7: If OE# is Low after new address input, read cycle is initiated. In other word, OE# must be brought to High
at the same time or before new address valid. Once read cycle is initiated, new write pulse should be input
after minimum t
RC
is met and data bus is in High-Z.
Parameter
Symbol
Value
Unit
Notes
Min.
Max.
Write Cycle Time
t
WC
70
1000
ns
*1, *2
Address Setup Time
t
AS
0
—
ns
*3
ADV# Low Pulse Width
t
VPL
10
—
ns
*4
Address Hold Time from ADV# High
t
AHV
5
—
ns
CE#1 Write Pulse Width
t
CW
45
—
ns
*3
WE# Write Pulse Width
t
WP
45
—
ns
*3
LB#, UB# Write Pulse Width
t
BW
45
—
ns
*3
CE#1 Write Recovery Time
t
WRC
15
—
ns
*5
WE# Write Recovery Time
t
WR
15
1000
ns
*5
LB#, UB# Write Recovery Time
t
BR
15
1000
ns
*5
Data Setup Time
t
DS
15
—
ns
Data Hold Time
t
DH
0
—
ns
OE# High to CE#1 Low Setup Time for Write
t
OHCL
–5
—
ns
*6
OE# High to Address Setup Time
for Write
t
OES
0
—
ns
*7
LB#, UB# Write Pulse Overlap
t
BWO
30
—
ns
CE#1 High Pulse Width
t
CP
15
—
ns
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| S71WS512N80BFIZZ0 | Stacked Multi-Chip Product (MCP) Flash Memory and pSRAM CMOS 1.8 Volt |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| S71WS512N80BFIZZ0 | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:Stacked Multi-Chip Product (MCP) Flash Memory and pSRAM CMOS 1.8 Volt |
| S71WS512N80BFIZZ2 | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:Stacked Multi-Chip Product (MCP) Flash Memory and pSRAM CMOS 1.8 Volt |
| S71WS512N80BFIZZ3 | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:Stacked Multi-Chip Product (MCP) Flash Memory and pSRAM CMOS 1.8 Volt |
| S71WS512N80BFWZZ0 | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:Stacked Multi-Chip Product (MCP) Flash Memory and pSRAM CMOS 1.8 Volt |
| S71WS512N80BFWZZ2 | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:Stacked Multi-Chip Product (MCP) Flash Memory and pSRAM CMOS 1.8 Volt |
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