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參數(shù)資料
| 型號： | S71WS512N80BFEZZ3 |
| 廠商： | Spansion Inc. |
| 英文描述： | Stacked Multi-Chip Product (MCP) Flash Memory and pSRAM CMOS 1.8 Volt |
| 中文描述： | 堆疊式多芯片產(chǎn)品（MCP）的閃存和移動存儲芯片的CMOS 1.8伏特 |
| 文件頁數(shù)： | 51/142頁 |
| 文件大小： | 1996K |
| 代理商： | S71WS512N80BFEZZ3 |
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June 28, 2004 S71WS512NE0BFWZZ_00_A1
S29WSxxxN MirrorBit Flash Family For Multi-chip Products (MCP)
51
A d v a n c e I n f o r m a t i o n
It is recommended that the wait state command sequence be written, even if the
default wait state value is desired, to ensure the device is set as expected. A
hardware reset will set the wait state to the default setting.
Programmable Wait State
If the device is equipped with the handshaking option, the host system should set
CR13-CR11
to 010 for a clock frequency of 54 MHz or to 011 for a clock fre-
quency of 66 MHz for the system/device to execute at maximum speed.
Table 14
describes the typical number of clock cycles (wait states) for various
conditions.
Boundary Crossing Latency
If the device is operating above 66 MHz, an additional wait state must be inserted
to account for boundary crossing latency. This is done by setting
CR14
to a ‘1’
(default). If the device is operating at or below 66 MHz, the additional wait state
for boundary crossing is not needed. Therefore the
CR14
can be changed to a ‘0’
to remove boundary crossing latency.
Set Internal Clock Frequency
The device switches at the full frequency of the external clock up to 66 MHz when
CR9
is set to a ‘1’ (default).
Handshaking
For optimal burst mode performance, the host system must set the appropriate
number of wait states in the flash device depending on the clock frequency.
The autoselect function allows the host system to determine whether the flash
device is enabled for handshaking. See the "
Autoselect Command Sequence
" sec-
tion for more information.
Table 13. Programmable Wait State Settings
CR13
0
0
0
0
1
1
1
1
CR12
0
0
1
1
0
0
1
1
CR11
0
1
0
1
0
1
0
1
Total Initial Access Cycles
2
3
4
5
6
7 (default)
Reserved
Reserved
Notes:
1. Upon power-up or hardware reset, the default setting is seven wait states.
2. RDY will default to being active with data when the Wait State Setting is set
to a total initial access cycle of 2.
Table 14. Wait States for Handshaking
Conditions at Address
Typical No. of Clock Cycles after AVD# Low
54
MHz
66
MHz
Initial address (V
IO
= 1.8 V)
4
5
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| S71WS512N80BFIZZ0 | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:Stacked Multi-Chip Product (MCP) Flash Memory and pSRAM CMOS 1.8 Volt |
| S71WS512N80BFIZZ2 | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:Stacked Multi-Chip Product (MCP) Flash Memory and pSRAM CMOS 1.8 Volt |
| S71WS512N80BFIZZ3 | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:Stacked Multi-Chip Product (MCP) Flash Memory and pSRAM CMOS 1.8 Volt |
| S71WS512N80BFWZZ0 | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:Stacked Multi-Chip Product (MCP) Flash Memory and pSRAM CMOS 1.8 Volt |
| S71WS512N80BFWZZ2 | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:Stacked Multi-Chip Product (MCP) Flash Memory and pSRAM CMOS 1.8 Volt |
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