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參數(shù)資料
| 型號(hào)： | S71WS512N80BAWZZ2 |
| 廠商： | Spansion Inc. |
| 英文描述： | Stacked Multi-Chip Product (MCP) Flash Memory and pSRAM CMOS 1.8 Volt |
| 中文描述： | 堆疊式多芯片產(chǎn)品（MCP）的閃存和移動(dòng)存儲(chǔ)芯片的CMOS 1.8伏特 |
| 文件頁(yè)數(shù)： | 58/142頁(yè) |
| 文件大?。?/td> | 1996K |
| 代理商： | S71WS512N80BAWZZ2 |
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58
S29WSxxxN MirrorBit Flash Family For Multi-chip Products (MCP)
S71WS512NE0BFWZZ_00_ A1 June 28, 2004
A d v a n c e I n f o r m a t i o n
quence, resulting in faster total programming time. The host system may also
initiate the chip erase and sector erase sequences in the unlock bypass mode. The
erase command sequences are four cycles in length instead of six cycles. The
"
Command Definition Summary
" section shows the requirements for the unlock
bypass command sequences.
During the unlock bypass mode, only the Read, Unlock Bypass Program, Unlock
Bypass Sector Erase, Unlock Bypass Chip Erase, and Unlock Bypass Reset com-
mands are valid. To exit the unlock bypass mode, the system must issue the two-
cycle unlock bypass reset command sequence. The first cycle must contain the
bank address and the data 90h. The second cycle need only contain the data 00h.
The bank then returns to the read mode.
The device offers accelerated program operations through the ACC input. When
the system asserts V
HH
on this input, the device automatically enters the Unlock
Bypass mode. The system may then write the two-cycle Unlock Bypass program
command sequence. The device uses the higher voltage on the ACC input to ac-
celerate the operation.
Figure 3
illustrates the algorithm for the program operation. Refer to the Erase/
Program Operations table in
“AC Characteristics—Asynchronous”
for parameters,
and
Figure 21
for timing diagrams.
Chip Erase Command Sequence
Chip erase is a six bus cycle operation or, in the unlock bypass mode, a four-cycle
operation. The chip erase command sequence is initiated by writing two unlock
cycles, followed by a set-up command. Two additional unlock write cycles are
then followed by the chip erase command, which in turn invokes the Embedded
Erase algorithm. The device does not require the system to preprogram prior to
Note:
See the "
Command Definition Summary
" section for program command sequence.
Figure 3. Program Operation
START
Write Program
Command Sequence
Data Poll
from System
Verify Data
No
Yes
Last Address
No
Yes
Programming
Completed
Increment Address
Embedded
Program
algorithm
in progress
相關(guān)PDF資料 |
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| S71WS512N80BAWZZ3 | Stacked Multi-Chip Product (MCP) Flash Memory and pSRAM CMOS 1.8 Volt |
| S71WS512N80BFEZZ0 | Stacked Multi-Chip Product (MCP) Flash Memory and pSRAM CMOS 1.8 Volt |
| S71WS512N80BFEZZ2 | Stacked Multi-Chip Product (MCP) Flash Memory and pSRAM CMOS 1.8 Volt |
| S71WS512N80BFEZZ3 | Stacked Multi-Chip Product (MCP) Flash Memory and pSRAM CMOS 1.8 Volt |
| S71WS512N80BFIZZ0 | Stacked Multi-Chip Product (MCP) Flash Memory and pSRAM CMOS 1.8 Volt |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| S71WS512N80BAWZZ3 | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:Stacked Multi-Chip Product (MCP) Flash Memory and pSRAM CMOS 1.8 Volt |
| S71WS512N80BFEZZ0 | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:Stacked Multi-Chip Product (MCP) Flash Memory and pSRAM CMOS 1.8 Volt |
| S71WS512N80BFEZZ2 | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:Stacked Multi-Chip Product (MCP) Flash Memory and pSRAM CMOS 1.8 Volt |
| S71WS512N80BFEZZ3 | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:Stacked Multi-Chip Product (MCP) Flash Memory and pSRAM CMOS 1.8 Volt |
| S71WS512N80BFIZZ0 | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:Stacked Multi-Chip Product (MCP) Flash Memory and pSRAM CMOS 1.8 Volt |
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