- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄365451 > S71WS512N80BAWZZ2 (Spansion Inc.) Stacked Multi-Chip Product (MCP) Flash Memory and pSRAM CMOS 1.8 Volt PDF資料下載
參數(shù)資料
| 型號： | S71WS512N80BAWZZ2 |
| 廠商： | Spansion Inc. |
| 英文描述： | Stacked Multi-Chip Product (MCP) Flash Memory and pSRAM CMOS 1.8 Volt |
| 中文描述： | 堆疊式多芯片產(chǎn)品（MCP）的閃存和移動存儲芯片的CMOS 1.8伏特 |
| 文件頁數(shù)： | 52/142頁 |
| 文件大?。?/td> | 1996K |
| 代理商： | S71WS512N80BAWZZ2 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁當(dāng)前第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁第115頁第116頁第117頁第118頁第119頁第120頁第121頁第122頁第123頁第124頁第125頁第126頁第127頁第128頁第129頁第130頁第131頁第132頁第133頁第134頁第135頁第136頁第137頁第138頁第139頁第140頁第141頁第142頁
52
S29WSxxxN MirrorBit Flash Family For Multi-chip Products (MCP)
S71WS512NE0BFWZZ_00_ A1 June 28, 2004
A d v a n c e I n f o r m a t i o n
Burst Sequence
Only sequential burst is allowed in the device.
CR7
defaults to a ‘1’ and must al-
ways be set to a ‘1’.
Burst Length Configuration
The device supports four different read modes: continuous mode, and 8, 16, and
32 word linear with or without wrap around modes. A continuous sequence (de-
fault) begins at the starting address and advances the address pointer until the
burst operation is complete. If the highest address in the device is reached during
the continuous burst read mode, the address pointer wraps around to the lowest
address.
For example, an eight-word linear read with wrap around begins on the starting
address written to the device and then advances to the next 8 word boundary.
The address pointer then returns to the 1st word after the previous eight word
boundary, wrapping through the starting location. The sixteen- and thirty-two lin-
ear wrap around modes operate in a fashion similar to the eight-word mode.
Table 15
shows the
CR2-CR0
and settings for the four read modes.
Burst Wrap Around
By default, the device will perform burst wrap around with
CR3
set to a ‘1’.
Changing the
CR3
to a ‘0’ disables burst wrap around.
Burst Active Clock Edge Configuration
By default, the device will deliver data on the rising edge of the clock after the
initial synchronous access time. Subsequent outputs will also be on the following
rising edges, barring any delays. The device can be set so that the falling clock
edge is active for all synchronous accesses.
CR6
determines this setting; “1” for
rising active (default), “0” for falling active.
RDY Configuration
By default, the device is set so that the RDY pin will output V
OH
whenever there
is valid data on the outputs. The device can be set so that RDY goes active one
data cycle before active data.
CR8
determines this setting; “1” for RDY active
(default) with data, “0” for RDY active one clock cycle before valid data. In asyn-
chronous mode, RDY is an open-drain output.
RDY Polarity
By default, the RDY pin will always indicate that the device is ready to handle a
new transaction with
CR10
set to a ‘1’ when high. In this case, the RDY pin is
active high. Changing the
CR10
to a ‘0’ sets the RDY pin to be active low. In this
Table 15. Burst Length Configuration
Burst Modes
Address Bits
CR2
CR1
CR0
Continuous
0
0
0
8-word linear
0
1
0
16-word linear
0
1
1
32-word linear
1
0
0
Note:
Upon power-up or hardware reset the default setting is continuous.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| S71WS512N80BAWZZ3 | Stacked Multi-Chip Product (MCP) Flash Memory and pSRAM CMOS 1.8 Volt |
| S71WS512N80BFEZZ0 | Stacked Multi-Chip Product (MCP) Flash Memory and pSRAM CMOS 1.8 Volt |
| S71WS512N80BFEZZ2 | Stacked Multi-Chip Product (MCP) Flash Memory and pSRAM CMOS 1.8 Volt |
| S71WS512N80BFEZZ3 | Stacked Multi-Chip Product (MCP) Flash Memory and pSRAM CMOS 1.8 Volt |
| S71WS512N80BFIZZ0 | Stacked Multi-Chip Product (MCP) Flash Memory and pSRAM CMOS 1.8 Volt |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| S71WS512N80BAWZZ3 | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:Stacked Multi-Chip Product (MCP) Flash Memory and pSRAM CMOS 1.8 Volt |
| S71WS512N80BFEZZ0 | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:Stacked Multi-Chip Product (MCP) Flash Memory and pSRAM CMOS 1.8 Volt |
| S71WS512N80BFEZZ2 | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:Stacked Multi-Chip Product (MCP) Flash Memory and pSRAM CMOS 1.8 Volt |
| S71WS512N80BFEZZ3 | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:Stacked Multi-Chip Product (MCP) Flash Memory and pSRAM CMOS 1.8 Volt |
| S71WS512N80BFIZZ0 | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:Stacked Multi-Chip Product (MCP) Flash Memory and pSRAM CMOS 1.8 Volt |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。