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參數(shù)資料
| 型號： | S71PL032J80BAW074 |
| 廠商： | SPANSION LLC |
| 元件分類： | 存儲器 |
| 英文描述： | SPECIALTY MEMORY CIRCUIT, PBGA56 |
| 封裝： | 7 X 9 MM, 1.20 MM HEIGHT, FBGA-56 |
| 文件頁數(shù)： | 116/188頁 |
| 文件大?。?/td> | 5078K |
| 代理商： | S71PL032J80BAW074 |
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32
S29PL127J/S29PL064J/S29PL032J for MCP
S29PL127_064_032J_00_A1 May 21, 2004
Prelimin ary
requires standard access time (tCE) for read access when the device is in either
of these standby modes, before it is ready to read data.
If the device is deselected during erasure or programming, the device draws ac-
tive current until the operation is completed.
ICC3 in “DC Characteristics” represents the CMOS standby current specification.
Automatic Sleep Mode
The automatic sleep mode minimizes Flash device energy consumption. The de-
vice automatically enables this mode when addresses remain stable for tACC +
30 ns. The automatic sleep mode is independent of the CE#, WE#, and OE# con-
trol signals. Standard address access timings provide new data when addresses
are changed. While in sleep mode, output data is latched and always available to
the system. Note that during automatic sleep mode, OE# must be at VIH before
Characteristics” represents the automatic sleep mode current specification.
RESET#: Hardware Reset Pin
The RESET# pin provides a hardware method of resetting the device to reading
array data. When the RESET# pin is driven low for at least a period of tRP, the
device immediately terminates any operation in progress, tristates all output
pins, and ignores all read/write commands for the duration of the RESET# pulse.
The device also resets the internal state machine to reading array data. The op-
eration that was interrupted should be reinitiated once the device is ready to
accept another command sequence, to ensure data integrity.
Current is reduced for the duration of the RESET# pulse. When RESET# is held
at VIL but not within VSS±0.3 V, the standby current will be greater.
The RESET# pin may be tied to the system reset circuitry. A system reset would
thus also reset the Flash memory, enabling the system to read the boot-up firm-
ware from the Flash memory.
If RESET# is asserted during a program or erase operation, the RY/BY# pin re-
mains a “0” (busy) until the internal reset operation is complete, which requires
a time of tREADY (during Embedded Algorithms). The system can thus monitor RY/
BY# to determine whether the reset operation is complete. If RESET# is asserted
when a program or erase operation is not executing (RY/BY# pin is “1”), the reset
operation is completed within a time of tREADY (not during Embedded Algorithms).
The system can read data tRH after the RESET# pin returns to VIH.
Refer to the AC Characteristic tables for RESET# parameters and to 13 for the
timing diagram.
Output Disable Mode
When the OE# input is at VIH, output from the device is disabled. The output pins
(except for RY/BY#) are placed in the highest Impedance state
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