
S5935 – PCI Product
Revision 1.02 – June 27, 2006
Data Book
AMCC Confidential and Proprietary
DS1527 79
ADD-ON PASS-THRU ADDRESS REGISTER (APTA)
Register
Name
Add-On Pass-Thru Address
This register is employed when a response is desired when one of the Base
address decode regions is selected during an active PCI bus cycle. When
one of the base address decode registers 1-4 encounters a PCI bus cycle
which selects the region defined by it, this device latches that current cycle’s
active address and asserts the signal PTATN# (Pass-Thru Attention). Wait
states are generated on the PCI bus until either data is transferred or the PCI
bus cycle is aborted by the initiator.
This register provides a method for “l(fā)ive” data (registered) transfers.
Intended uses include the emulating of other hardware as well as enabling
the connection of existing external hardware to interface to the PCI bus
through the S5935.
Add-On
Address
Offset
28h
Power-up
value
XXXXXXXXh
Attribute
Read Only
Size
32 bits
ADD-ON PASS-THRU DATA REGISTER (APTD)
Register Name
Add-On Pass-Thru Data
This register, along with APTA described above, is employed when a
response is desired should one of the Base address decode regions become
selected during an active PCI bus cycle. When one of the base address
decode registers 1-4 encounters a PCI bus cycle which selects the region
defined by it, the APTA register will contain that current cycle’s active address
and the device asserts the signal PTATN# (Pass-Thru ATentioN). Wait states
are generated on the PCI bus until this register is read (PCI bus writes) or this
register is written (PCI bus reads).
Add-On
Address Offset
2Ch
Power-up value
XXXXXXXXh
Attribute
Read/Write
Size
32 bits