
RESET and POWER-DOWN 
S3C94A5/F94A5 
8-2 
POWER-DOWN MODES 
STOP MODE 
Stop mode is invoked by the instruction STOP. In Stop mode, the operation of the CPU and all peripherals is halted. 
That is, the on-chip main oscillator stops and the supply current is reduced to less than 2
μ
A. All system functions 
stop when the clock "freezes", but data stored in the internal register file is retained. Stop mode can be released in 
one of two ways: by a reset or by external interrupts. 
Example: 
LD 
STOP 
NOP 
NOP 
NOP 
LD 
STPCON,#10100101B 
STPCON,#00000000B 
NOTES 
1. Do not use stop mode if you are using an external clock source because X
IN
 input must be restricted    
    internally to V
SS
 to reduce current leakage. 
2. In application programs, a STOP instruction must be immediately followed by at least three NOP 
instructions. This ensures an adequate time interval for the clock to stabilize before the next  
instruction is executed. If three or more NOP instructions are not used after STOP instruction,  
    leakage current could be flown because of the floating state in the internal bus. 
3. To enable/disable STOP instruction, the STPCON register should be written with 10100101B/other  
values before/after stop instruction. 
Using nRESET to Release Stop Mode 
Stop mode is released when the
nRESET
signal goes active (Low level): all system and peripheral control registers 
are reset to their default hardware values and the contents of all data registers are retained. When the programmed 
oscillation stabilization interval has elapsed, the CPU starts the system initialization routine by fetching the program 
instruction stored in ROM location 0100H.  
Using an External Interrupt to Release Stop Mode 
External interrupts can be used to release stop mode. For the S3C94A5 microcontroller, we recommend using the 
INT interrupt, P1, P3, P4.7, and P5.0.