
MMC/SD/SDIO CONTROLLER
S3C2440A RISC MICROPROCESSOR
19-14
SDI Interrupt Mask Register (SDIIntMsk) (Continued)
SDIIntMsk
Bit
Description
Initial Value
BusyFin Interrupt
Enable (BusyFinInt)
[6]
Determines SDI generate an interrupt if only busy check
completes
0 = Disable, 1 = Interrupt enable
0
Reserved
[5]
–
0
TFHalf Interrupt
Enable (TFHalfInt)
[4]
Determines SDI generate an interrupt if Tx FIFO fills half
0 = Disable, 1 = Interrupt enable
0
TFEmpty Interrupt
Enable (TFEmptInt)
[3]
Determines SDI generate an interrupt if Tx FIFO is empty
0 = Disable, 1 = Interrupt enable
0
RFLast Interrupt
Enable (RFLastInt)
[2]
Determines SDI generate an interrupt if Rx FIFO has last data
0 = Disable, 1 = Interrupt enable
0
RFFull Interrupt
Enable (RFFullInt)
[1]
Determines SDI generate an interrupt if Rx FIFO fills full
0 = Disable, 1 = Interrupt enable
0
RFHalf Interrupt
Enable (RFHalfInt)
[0]
Determines SDI generate an interrupt if Rx FIFO fills half
0 = Disable, 1 = Interrupt enable
0
SDI Data Register (SDIDAT)
Register
Address
R/W
Description
Reset Value
SDIDAT
0x5A000040, 44, 48,
4C(Li/W, Li/HW, Li/B, Bi/W)
0x5A000041(Bi/HW),
0x5A000043(Bi/B)
R/W
SDI data register
0x0
SDIDAT
Bit
Description
Initial State
Data Register
[31:0]
This field contains the data to be transmitted or received over the
SDI channel
0x00000000
NOTE:
—
—
—
—
(Li/W, Li/HW, Li/B): Access by Word/HalfWord//Byte unit when endian mode is Little
(Bi/W): Access by Word unit when endian mode is Big
(Bi/HW): Access by HalfWord unit when endian mode is Big
(Bi/B): Access by Byte unit when endian mode is Big