
S3C2440A MICROCONTROLLER
xxix
List of Tables
Table
Number
Title
Page
Number
1-1
1-2
1-3
1-4
289-Pin FBGA Pin Assignments – Pin Number Order (Sheet 1 of 3).....................................1-7
S3C2440A 289-Pin FBGA Pin Assignments (Sheet 1 of 9)..................................................1-10
S3C2440A Signal Descriptions (Sheet 1 of 6).....................................................................1-20
S3C2440A Special Registers (Sheet 1 of 14) .....................................................................1-26
2-1
2-2
2-3
PSR Mode Bit Values......................................................................................................2-9
Exception Entry/Exit........................................................................................................2-11
Exception Vectors...........................................................................................................2-13
3-1
3-2
3-3
3-4
3-5
3-6
The ARM Instruction Set ..................................................................................................3-2
Condition Code Summary.................................................................................................3-4
ARM Data Processing Instructions....................................................................................3-11
Incremental Cycle Times..................................................................................................3-16
Assembler Syntax Descriptions........................................................................................3-27
Addressing Mode Names .................................................................................................3-45
4-1
4-2
4-3
4-4
4-5
4-6
4-7
4-8
4-9
4-10
4-11
4-12
4-13
4-14
4-15
4-16
4-17
4-18
4-19
4-20
THUMB Instruction Set Opcodes ......................................................................................4-3
Summary of Format 1 Instructions ....................................................................................4-5
Summary of Format 2 Instructions ....................................................................................4-7
Summary of Format 3 Instructions ....................................................................................4-9
Summary of Format 4 Instructions ....................................................................................4-11
Summary of Format 5 Instructions ....................................................................................4-13
Summary of PC-Relative Load Instruction ..........................................................................4-16
Summary of Format 7 Instructions ....................................................................................4-19
Summary of Format 8 Instructions ....................................................................................4-20
Summary of Format 9 Instructions ....................................................................................4-23
Halfword Data Transfer Instructions ...................................................................................4-24
SP-Relative Load/Store Instructions ..................................................................................4-26
Load Address..................................................................................................................4-28
The ADD SP Instruction...................................................................................................4-30
PUSH and POP Instructions.............................................................................................4-31
The Multiple Load/Store Instructions..................................................................................4-33
The Conditional Branch Instructions ..................................................................................4-34
The SWI Instruction.........................................................................................................4-36
Summary of Branch Instruction.........................................................................................4-37
The BL Instruction ...........................................................................................................4-39
5-1
5-2
Bank 6/7 Addresses ........................................................................................................5-3
SDRAM Bank Address Configuration Example...................................................................5-5
7-1
7-2
7-3
7-4
Clock Source Selection at Boot-Up...................................................................................7-2
Clock and Power State in Each Power Mode .....................................................................7-11
CLKSLOW and CLKDIVN Register Settings for SLOW Clock example.................................7-12
Pin configuration table in Sleep mode................................................................................7-16