
NAND FLASH CONTROLLER
S3C2440A RISC MICROPROCESSOR
6-12
NAND FLASH CONFIGURATION REGISTER
Register
Address
R/W
Description
Reset Value
NFCONF
0x4E000000
R/W
NAND flash configuration register
0x0000100X
NFCONF
Bit
Description
Initial State
–
01
Reserved
TACLS
[15:14]
[13:12]
Reserved
CLE & ALE duration setting value (0~3)
Duration = HCLK x TACLS
Reserved
TWRPH0 duration setting value (0~7)
Duration = HCLK x ( TWRPH0 + 1 )
Reserved
TWRPH1 duration setting value (0~7)
Duration = HCLK x ( TWRPH1 + 1 )
Advance NAND flash memory for auto-booting
0: Support 256 or 512 byte/page NAND flash memory
1: Support 1024 or 2048 byte/page NAND flash memory
This bit is determined by NCON0 pin status during reset
and wake-up from sleep mode.
NAND flash memory page size for auto-booting AdvFlash
PageSize
When AdvFlash is 0,
0: 256 Word/page,
1: 512 Bytes/page
When AdvFlash is 1,
0: 1024 Word/page,
1: 2048 Bytes/page
This bit is determined by GPG13 pin status during reset
and wake-up from sleep mode. After reset, the GPG13 can
be used as general I/O port or External interrupt.
NAND flash memory Address cycle for auto-booting
AdvFlash AddrCycle
When AdvFlash is 0,
0: 3 address cycle
1: 4 address cycle
When AdvFlash is 1,
0: 4 address cycle
1: 5 address cycle
This bit is determined by GPG14pin status during reset
and wake-up from sleep mode. After reset, the GPG14can
be used as general I/O port or External interrupt.
NAND Flash Memory I/O bus width for auto-booting and
general access.
0: 8-bit bus
1: 16-bit bus
This bit is determined by GPG15 pin status during reset
and wake-up from sleep mode.
After reset, the GPG15 can be used as general I/O port or
External interrupt.
This bit can be changed by software.
Reserved
TWRPH0
[11]
[10:8]
0
000
Reserved
TWRPH1
[7]
[6:4]
0
000
AdvFlash (Read only)
[3]
H/W Set
(NCON0)
PageSize (Read only)
[2]
H/W Set
(GPG13)
AddrCycle (Read only)
[1]
H/W Set
(GPG14)
BusWidth (R/W)
[0]
H/W Set
(GPG15)