
S3C2440A MICROCONTROLLER
xxv
List of Figures
(Continued)
Figure
Number
Title
Page
Number
6-1
6-2
6-3
6-4
6-5
6-6
6-7
6-8
NAND Flash Controller Block Diagram...............................................................................6-2
NAND Flash Controller Boot Loader Block Diagram............................................................6-2
CLE & ALE Timing (TACLS=1, TWRPH0=0, TWRPH1=0)...................................................6-4
nWE & nRE Timing (TWRPH0=0, TWRPH1=0)..................................................................6-4
NAND Flash Memory Mapping..........................................................................................6-9
A 8-bit NAND Flash Memory Interface...............................................................................6-10
Two 8-bit NAND Flash Memory Interface............................................................................6-10
A 16-bit NAND Flash Memory Interface.............................................................................6-11
7-1
7-2
7-3
7-4
7-5
7-6
7-7
7-8
7-9
7-10
7-11
Clock Generator Block Diagram........................................................................................7-3
PLL (Phase-Locked Loop) Block Diagram..........................................................................7-5
Main Oscillator Circuit Examples ......................................................................................7-5
Power-On Reset Sequence (when the external clock source is a crystal oscillator) ...............7-6
Changing Slow Clock by Setting PMS Value......................................................................7-7
Example of Internal Clock Change.....................................................................................7-8
The Clock Distribution Block Diagram................................................................................7-10
Power Management State Diagram...................................................................................7-11
Issuing Exit_from_Slow_mode Command in PLL on State...................................................7-13
Issuing Exit_from_Slow_mode Command After Lock Time...................................................7-13
Issuing Exit_from_Slow_mode Command and the Instant PLL_on
Command Simultaneously................................................................................................7-14
SLEEP Mode..................................................................................................................7-17
7-12
8-1
8-2
8-3
8-4
8-5
8-6
Basic DMA Timing Diagram..............................................................................................8-3
Demand/Handshake Mode Comparison.............................................................................8-4
Burst 4 Transfer Size.......................................................................................................8-5
Single service in Demand Mode with Unit Transfer Size.......................................................8-6
Single service in Handshake Mode with Unit Transfer Size..................................................8-6
Whole service in Handshake Mode with Unit Transfer Size..................................................8-6
10-1
10-2
10-3
10-4
10-5
10-6
10-7
10-8
16-bit PWM Timer Block Diagram.....................................................................................10-2
Timer Operations.............................................................................................................10-3
Example of Double Buffering Function ...............................................................................10-4
Example of a Timer Operation...........................................................................................10-6
Example of PWM............................................................................................................10-7
Inverter On/Off.................................................................................................................10-8
The Wave Form When a Dead Zone Feature is Enabled......................................................10-9
Timer4 DMA Mode Operation............................................................................................10-10