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參數(shù)資料
| 型號： | S3C1850XX-SM |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 4-BIT, MROM, 6 MHz, MICROCONTROLLER, PDSO24 |
| 封裝： | 0.375 INCH, SOP-24 |
| 文件頁數(shù)： | 8/89頁 |
| 文件大?。?/td> | 323K |
| 代理商： | S3C1850XX-SM |
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S3C1850
2-15
RESET
All reset operations are internal in the S3C1850. It has an internal power-on reset circuit consisting of a 7 pF
capacitor and a 1 M
resistor (See Figure 2-17). The controller also contains an auto-reset circuit that resets the
chip every 131,072 oscillator clock cycles (288 ms at a fxx = 455KHz clock frequency). The auto-reset counter is
cleared by the rising edge of a internal P2.0 pin, by HALT, or by the power-on reset pulse (See Figure 2-18).
Therefore, no clocks are sent to the counter and the time-out is suspended in HALT mode. When a reset occurs
during program execution, a transient condition occurs. The PA register is immediately initialized to 0FH. The
PC, however, is not reset to 0H until one instruction cycle later. For example, if PC is 1AH when a reset pulse is
generated, the instruction at 0F1AH is executed, followed by the instruction at 0F00H.
After a reset, approximately 13 msec is needed before program execution proceeds (assuming fxx = 455 kHz
ceramic oscillation).
Upon initialization, registers are set as follows:
PC register to 0 in next instruction cycle
PA and PB registers to 0FH (15th page)
SF and SL registers to 1
HL registers to unknown state
All internal/external output pins (P3.0-P3.3, P2.1-P2.6, P2.9, P2.10, P2.12 and P2.13 except P2.0/REM) to
low.
1 M
VDD
VSS
S3C1850
7 pF
Figure 2-17. S3C1850's Power-on Reset Circuit
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