參數(shù)資料
型號(hào): S3C1850XX-SM
元件分類: 微控制器/微處理器
英文描述: 4-BIT, MROM, 6 MHz, MICROCONTROLLER, PDSO24
封裝: 0.375 INCH, SOP-24
文件頁(yè)數(shù): 35/89頁(yè)
文件大?。?/td> 323K
代理商: S3C1850XX-SM
INSTRUCTION SET
S3C1840/C1850/C1860/P1860
5-18
DECS
A,@HL
Binary Code:
0 0 0 0
0 1 1 1
Description:
The contents of the data memory addressed by the H and L registers are decremented by
one and the result is loaded in the accumulator.
But the contents of data memory are not affected.
Operation:
(A)
← M [(H,L)] - 1
Flags:
SF : Set if a carry occurred, cleared otherwise
SL : Unaffected
Example:
Assume RAM address holds 5h
MOV
L,#0AH
MOV
A,L
DECS
A,@HL
; Decrement the value 5H by one, and the result value 4H is
loaded in A
DECS
L
Binary Code:
0 0 0 0
0 1 0 0
Description:
The contents of the L register are decremented by one.
Operation:
(L)
← (L) - 1
Flags:
SF : Set if no borrow occurred, cleared otherwise
SL : Unaffected
Example:
MOV
L,#3H
DECS
L
; This instruction leaves the value 2H in REG L
SETB
@HL,b
Binary Code:
0 0 1 1
0 0 d d
Description:
This instruction sets indirect data memory bit addressed by registers H and L without
affecting any other bits in the destination.
Operation:
b
← 1 (b = 0,1,2,3)
Flags:
SF : Set to one
SL : Unaffected
Example:
MOV
H,#0H
MOV
L,#5H
SETB
@HL.2
; Set RAM address 05H bit 2 to 1
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