參數(shù)資料
型號： S3C1850XX-SM
元件分類： 微控制器/微處理器
英文描述： 4-BIT, MROM, 6 MHz, MICROCONTROLLER, PDSO24
封裝： 0.375 INCH, SOP-24
文件頁數(shù)： 30/89頁
文件大?。?/td> 323K
代理商： S3C1850XX-SM
INSTRUCTION SET
S3C1840/C1850/C1860/P1860
5-14
OUT
P3,@SL+A
Binary Code:
0 0 0 0
1 0 1 0
Description:
The contents of the accumulator and SL are transferred to the P3 Output register.
Operation:
(P3 Output register)
← (A) + (SL)
Flags:
SF : Set to one
SL : Unaffected
Example:
CLR
A
OUT
P3,@SL+A
; Zero output on port 3
NOTI
A
Binary Code:
0 0 1 1
1 1 0 1
Description:
The contents of the accumulator are complemented; all 1 bits are changed to 0, and vice-
versa, and then incremented by one.
Operation:
(A)
← (A), (A) ← (A) +1
Flags:
SF : Set if the result is zero, cleared otherwise
SL : Unaffected
Example:
CLR
A
ADDS
A,#7H
NOTI
A
; Complement 7H (0111B) and increment the result by one;
the instruction NOTI A then leaves 9H (1001B) in A
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