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參數(shù)資料
| 型號(hào)： | S3050 |
| 廠商： | Applied Micro Circuits Corp. |
| 英文描述： | Multi-Rate SONET/SDH Clock Recovery Unit(多速率SONET/SDH時(shí)鐘恢復(fù)單元) |
| 中文描述： | 多速率SONET / SDH時(shí)鐘恢復(fù)單元（多速率SONET / SDH的時(shí)鐘恢復(fù)單元） |
| 文件頁(yè)數(shù)： | 4/17頁(yè) |
| 文件大?。?/td> | 132K |
| 代理商： | S3050 |
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4
S3050
MULTI-RATE SONET/SDH CLOCK RECOVERY UNIT
July 9, 1999 / Revision D
Figure 3. Input Jitter Tolerance Specification
Figure 4. Jitter Transfer Specification
1. Bellcore Specifications: GR-253- CORE, Issue 2,
December 1995.
2. ITU-T Recommendations: G.958.
3. Not specified in GR-253 or G.958.
f0
f1
f2
f3
ft
0.15
1.5
15
Sinusodal
Input Jitter
Amplitude
(UI p-p)
Frequency
fc
P
Jitter
Transfer
Frequency
Acceptable
Range
slope = -20 dB/decade
CHARACTERISTICS
Performance
The S3050 PLL complies with the jitter specifications
proposed for SONET/SDH equipment defined by the
Bellcore Specifications: GR-253-CORE, Issue 2, De-
cember 1995 and ITU-T Recommendations: G.958
document, when used with differential inputs and out-
puts.
Input Jitter Tolerance
Input jitter tolerance is defined as the peak to
peak amplitude of sinusoidal jitter applied on the
input signal that causes an equivalent 1 dB opti-
cal/electrical power penalty. SONET input jitter
tolerance requirements are shown in Figure 3.
The measurement condition is the input jitter am-
plitude which causes an equivalent of 1 dB power
penalty.
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1
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2
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3
H
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k
t
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k
8
4
0
1
0
0
6
0
0
0
6
0
0
1
0
0
0
1
4
2
1
2
1
0
1
0
3
0
0
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5
2
0
5
2
3
0
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0
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0
0
3
5
5
6
S
T
2
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0
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2
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0
0
5
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3
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2
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1
1. Not specified in GR-253 and G.958.
Jitter Transfer
Jitter transfer function is defined as the ratio of jitter
on the output OC-N/STS-N signal to the jitter applied
on the input OC-N/STS-N signal versus frequency.
Jitter transfer requirements are shown in Figure 4.
The measurement condition is that input sinusoidal
jitter up to the mask level in Figure 3 be applied.
Jitter Generation
The jitter of the serial clock and serial data outputs
shall not exceed 0.01 UI rms when a serial data input
with no jitter is presented to the serial data inputs.
(See Table 4).
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