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參數(shù)資料
| 型號： | S3050 |
| 廠商： | Applied Micro Circuits Corp. |
| 英文描述： | Multi-Rate SONET/SDH Clock Recovery Unit(多速率SONET/SDH時鐘恢復單元) |
| 中文描述： | 多速率SONET / SDH時鐘恢復單元（多速率SONET / SDH的時鐘恢復單元） |
| 文件頁數(shù)： | 1/17頁 |
| 文件大小： | 132K |
| 代理商： | S3050 |
1
S3050
S3050
BiCMOS PECL CLOCK GENERATOR
July 9, 1999 / Revision D
DEVICE
SPECIFICATION
FEATURES
Micro-power Bipolar technology
Complies with Bellcore and ITU-T specifica-
tions for jitter tolerance, jitter transfer and
jitter generation
On-chip high frequency PLL with internal
loop filter for clock recovery
Supports clock recovery for:
OC-48 (2488.32 Mbps),
OC-24 (1244.16 Mbps),
Gigabit Ethernet (1250 Mbps),
OC-12 (622.08 Mbps),
OC-3 (155.52 Mbps)
NRZ data
155.52 MHz reference frequency
Lock detect—monitors frequency
Low-jitter serial interface
+5V supply
32 TQFP/TEP package
GENERAL DESCRIPTION
The function of the S3050 clock recovery unit is to
derive high speed timing signals for SONET/SDH-
based equipment. The S3050 is implemented using
AMCC’s proven Phase Locked Loop (PLL) technology.
The S3050 receives an OC-48, OC-24, GBE, OC-
12, or OC-3 scrambled NRZ signal and recovers
the clock from the data. The chip outputs a differ-
ential bit clock and retimed data. Figure 1 shows a
typical network application.
The S3050 utilizes an on-chip PLL which consists
of a phase detector, a loop filter, and a voltage
controlled oscillator (VCO). The phase detector
compares the phase relationship between the VCO
output and the serial data input. A loop filter con-
verts the phase detector output into a smooth DC
voltage, and the DC voltage is input to the VCO
whose frequency is varied by this voltage. A func-
tional block diagram is shown in Figure 2.
Figure 1. System Block Diagram
N
P
S
S3041
Tx
S3042
Rx
S3042
Rx
S3041
Tx
OTX
ORX
OTX
ORX
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
N
P
S
S3050
S3050
This product is not released
and the specifications herein
are subject to change.
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