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參數(shù)資料
| 型號： | S3059 |
| 廠商： | Applied Micro Circuits Corp. |
| 英文描述： | Multi-Rate SONET/SDH/ATM Transceiver(帶片上鎖相環(huán)的多速率SONET/SDH/ATM收發(fā)器) |
| 中文描述： | 多速率SONET / SDH / ATM的收發(fā)器（帶片上鎖相環(huán)的多速率的SONET / SDH / ATM的收發(fā)器） |
| 文件頁數(shù)： | 1/28頁 |
| 文件大小： | 203K |
| 代理商： | S3059 |
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S3059
S3059
MULTI-RATE (OC-48/24/12/3/GBE) SONET/SDH/ATM TRANSCEIVER
October 31, 2000 / Revision B
DEVICE
SPECIFICATION
FEATURES
SiGe BiCMOS technology
Complies with Bellcore and ITU-T
specifications
On-chip high-frequency PLL for clock
generation
Supports OC-48 (2488.32 Mbps)
OC-24 (1244.16 Mbps)
Gigabit Ethernet (1250 Mbps)
OC-12 (622.08 Mbps)
OC-3 (155.52 Mbps)
Reference frequency of 155.52 MHz
Interface to LVPECL and LVTTL logic
16-bit differential LVPECL datapath
Compact 218 TBGA package
Diagnostic loopback mode
Supports line timing
Lock detect
Signal detect input
Low jitter LVPECL interface
Internal FIFO to decouple transmit clocks
Single 3.3 V supply
Typical power 1.7 W
APPLICATIONS
Wavelength Division Multiplexing (WDM)
equipment
SONET/SDH-based transmission systems
SONET/SDH modules
SONET/SDH test equipment
ATM over SONET/SDH
Section repeaters
Add Drop Multiplexers (ADM)
Broad-band cross-connects
Fiber optic terminators
Fiber optic test equipment
Figure 1. System Block Diagram
GENERAL DESCRIPTION
The S3059 SONET/SDH transceiver chip is a fully
integrated serialization/deserialization SONET
OC-48 (2488.32 Mbps), OC-24 (1244.16 Mbps), Gi-
gabit Ethernet (1250 Mbps), OC-12 (622.08 Mbps)
and OC-3 (155.52 Mbps) interface device. The chip
performs all necessary serial-to-parallel and parallel-
to-serial functions in conformance with SONET/SDH
transmission standards. The device is suitable for
SONET-based WDM applications. Figure 1 shows a
typical network application.
On-chip clock synthesis is performed by the high-
frequency Phase Locked Loop (PLL) on the S3059
transceiver chip allowing the use of a slower external
transmit clock reference. The chip can be used with
a 155.52 MHz reference clock in support of existing
system clocking schemes.
The low jitter LVPECL interface guarantees compli-
ance with the bit-error rate requirements of the
Bellcore and ITU-T standards. The S3059 is pack-
aged in a 218 TBGA, offering designers a small
package outline.
N
P
N
P
S3059
S3059
OTX
ORX
OTX
ORX
16
16
16
16
S3056
S3056
RX
TX
TX
RX
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