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參數(shù)資料
| 型號： | S3050 |
| 廠商： | Applied Micro Circuits Corp. |
| 英文描述： | Multi-Rate SONET/SDH Clock Recovery Unit(多速率SONET/SDH時鐘恢復(fù)單元) |
| 中文描述： | 多速率SONET / SDH時鐘恢復(fù)單元（多速率SONET / SDH的時鐘恢復(fù)單元） |
| 文件頁數(shù)： | 3/17頁 |
| 文件大?。?/td> | 132K |
| 代理商： | S3050 |
3
S3050
MULTI-RATE SONET/SDH CLOCK RECOVERY UNIT
July 9, 1999 / Revision D
S3050 FUNCTIONAL DESCRIPTION
The S3050 clock recovery device performs the clock
recovery function for SONET OC-48, OC-24, Gigabit
Ethernet, OC-12, or OC-3 serial data links. The chip
extracts the clock from the serial data inputs and
provides retimed clock and data outputs. A 155.52
MHz (156.25 for Gigabit Ethernet) reference clock is
required for phase locked loop start up and proper
operation under loss of signal conditions. An integral
prescaler and phase locked loop circuit is used to
multiply this reference to the nominal bit rate. The
input data rate is selected by the RATESEL[1:0]
inputs. (See Table 1.)
Clock Recovery
Clock Recovery, as shown in the block diagram in
Figure 2, generates a clock that is at the same fre-
quency as the incoming data bit rate at the serial
data input. The clock is phase aligned by a PLL so
that it samples the data in the center of the data eye
pattern.
The phase relationship between the edge transi-
tions of the data and those of the generated clock
are compared by a phase/frequency discriminator.
Output pulses from the discriminator indicate the
required direction of phase corrections. These
pulses are smoothed by an integral loop filter. The
output of the loop filter controls the frequency of
the Voltage Controlled Oscillator (VCO), which
generates the recovered clock.
Frequency stability without incoming data is guaran-
teed by an alternate reference input (REFCLKP/N)
that the PLL locks onto when data is lost. If the Fre-
quency of the incoming signal is not within the range
stated in Table 4 with respect to REFCLKP/N, the PLL
will be declared out of lock, and the PLL will lock to the
reference clock. The assertion of Signal Detect (SDN)
will also cause an out of lock condition.
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Table 1. Data Rate Select
The loop filter transfer function is optimized to enable
the PLL to track the jitter, yet tolerate the minimum
transition density expected in a received SONET
data signal. This transfer function yields a typical
capture time as stated in Table 4 for random incom-
ing NRZ data.
The total loop dynamics of the clock recovery PLL
yield a jitter tolerance which exceeds the minimum
tolerance proposed for SONET equipment by the
Bellcore TA-NWT-000253 standard, shown in Figure 3.
Lock Detect
The S3050 contains a lock detect circuit which monitors
the integrity of the serial data inputs. If the received
serial data fails the frequency test, the PLL will be
forced to lock to the local reference clock. This will
maintain the correct frequency of the recovered clock
output under loss of signal or loss of lock conditions. If
the recovered clock frequency deviates from the local
reference clock frequency by more than the value
stated in Table 4, the PLL will be declared out of lock.
The lock detect circuit will poll the input data stream in
an attempt to reacquire lock to data. If the recovered
clock frequency is determined to be within the specifi-
cation as in Table 4, the PLL will be declared in lock
and the lock detect output will go active.
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