- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄374665 > S3038 (Applied Micro Circuits Corp.) SONET/SDH/ATM OC-12 Quad Transceiver(SONET/SDH四收發(fā)器（完全集成OC-12接口器件）) PDF資料下載
參數(shù)資料
| 型號： | S3038 |
| 廠商： | Applied Micro Circuits Corp. |
| 英文描述： | SONET/SDH/ATM OC-12 Quad Transceiver(SONET/SDH四收發(fā)器（完全集成OC-12接口器件）) |
| 中文描述： | 的SONET / SDH / ATM的的OC - 12四路收發(fā)器（SONET / SDH的四收發(fā)器（完全集成的OC - 12接口器件）） |
| 文件頁數(shù)： | 8/29頁 |
| 文件大?。?/td> | 1467K |
| 代理商： | S3038 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁當前第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁
8
S3038
SONET/SDH/ATM OC-12 QUAD TRANSCEIVER
May 31, 2001 / Revision C
FUNCTIONAL DESCRIPTION
QUAD TRANSMITTER OPERATION
The S3038 quad transceiver chip performs the seri-
alizing stage in the processing of a transmit SONET
STS-12 bit serial data stream. It converts the 8-bit
parallel 77.76 Mbyte/sec data stream into a bit serial
format at 622.08 Mbps.
A high-frequency bit clock can be generated from a
77.76 MHz frequency reference by using an integral
frequency synthesizer consisting of a phase-lock
loop circuit with a divider in the loop.
Diagnostic loopback is provided (transmitter to re-
ceiver). See Other Operating Modes.
Clock Synthesizer
The clock synthesizer is a monolithic PLL that gener-
ates the serial output clock phase synchronized with
the input reference clock (REFCLK).
The REFCLK input must be generated from a crys-
tal oscillator which has a frequency accuracy that
meets the value stated in Table 11.
The on-chip PLL consists of a phase detector, which
compares the phase relationship between the VCO
output and the REFCLK input, a loop filter which
converts the phase detector output into a smooth DC
voltage, and a VCO, whose frequency is varied by
this voltage.
The loop filter generates a VCO control voltage
based on the average DC level of the phase discrimi-
nator output pulses. A single external clean-up
capacitor is utilized as part of the loop filter. The loop
filter’s corner frequency is optimized to minimize out-
put phase jitter.
Timing Generator
The timing generation function provides an 8-bit par-
allel rate version of the transmit serial clock. This
circuitry also provides an internally generated load sig-
nal, which transfers the PIN[7:0] data from the
parallel input register to the serial shift register.
The PCLK output is an 8-bit parallel rate version of
the transmit serial clock at 77.76 MHz. PCLK is in-
tended for use as an 8-bit parallel clock for upstream
multiplexing and overhead processing circuits. Using
PCLK for upstream circuits will ensure a stable fre-
quency and phase relationship between the data
coming into and leaving the S3038 device.
Parallel-to-Serial Converter
The parallel-to-serial converter is comprised of two
8-bit parallel registers. The first register latches the
data from the PIN[7:0] bus on the rising edge of
PICLK. The second register is a parallel loadable
shift register which takes its parallel input from the
first register.
The load signal, which latches the data from the par-
allel to the serial shift register, has a fixed relationship
to PCLK. If PICLK is tied to PCLK, the PIN[7:0] data
latched into the parallel register will meet the timing
specifications with respect to the load signal. If PICLK
is not tied to PCLK, the delay must meet the timing
requirements.
Redundant Outputs
Two high-speed differential outputs are provided for
each channel. This enables each channel to drive a
primary and secondary switch fabric for SONET ap-
plications in which redundancy is required to achieve
higher reliability.
Routing of Signals for Channel-Lock Operation
When operating in the Channel Lock (CH_LOCK)
Mode, the user must ensure that the path length of
the four high-speed serial data signals are matched
to within
±
3 ns of delay. Failure to meet this require-
ment may result in bit errors in the received data or
in byte misalignment.
Table 2. Reference Frequency Options
e
r
e
R
e
r
F
Table 3. Reference Jitter Limits
e
R
m
u
m
i
a
M
t
z
H
k
2
1
n
r
e
d
n
k
c
a
o
C
z
H
e
c
M
n
5
e
r
o
B
g
n
r
d
o
e
p
M
O
e
s
m
r
s
p
4
1
2
1
–
S
T
S
L
E
S
K
L
C
k
c
o
C
y
c
n
e
e
c
u
n
q
g
n
r
d
o
e
p
M
O
e
1
z
H
M
8
8
3
2
1
S
T
S
0
z
H
M
6
7
7
2
1
S
T
S
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| S3040A | SONET/SDH Clock Recovery Unit(帶片上高頻鎖相環(huán)的SONET/SDH時鐘恢復單元) |
| S3040B | SONET/SDH Clock Recovery Unit(帶片上高頻鎖相環(huán)的SONET/SDH時鐘恢復單元) |
| S3040 | OC-48 Clock Recovery Unit(OC-48時鐘恢復單元) |
| S3041 | SONET/SDH/ATM OC-48 8:1 Transmitter(帶片上高頻鎖相環(huán)的8選1 SONET/SDH傳送器（集成SONET OC-48接口器件）) |
| S3042 | SONET/SDH/ATM OC-48 1：8 Receiver(帶片上高頻鎖相環(huán)的1：8 SONET/SDH接收器（集成SONET OC-48接口器件）) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| S3038TB | 制造商:AppliedMicro 功能描述: |
| S30395-1-G | 制造商: 功能描述: 制造商:undefined 功能描述: |
| S30395-513G | 制造商: 功能描述: 制造商:undefined 功能描述: |
| S303AB | 制造商:Cinch Connectors 功能描述:Conn Wire to Board SKT 3 POS Solder Lug ST Panel Mount |
| S-303-AB | 功能描述:Jones 插頭和插槽 3C PNL MNT SOCKET RoHS:否 制造商:Molex 產(chǎn)品類型:Socket Connectors 系列:Beau 位置/觸點數(shù)量:8 電壓額定值:250 V 電流額定值:10 A 外殼材料:Thermoplastic 觸點材料:Phosphor Bronze 觸點電鍍:Tin-Lead |
發(fā)布緊急采購，3分鐘左右您將得到回復。