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參數(shù)資料
| 型號(hào)： | S3038 |
| 廠商： | Applied Micro Circuits Corp. |
| 英文描述： | SONET/SDH/ATM OC-12 Quad Transceiver(SONET/SDH四收發(fā)器（完全集成OC-12接口器件）) |
| 中文描述： | 的SONET / SDH / ATM的的OC - 12四路收發(fā)器（SONET / SDH的四收發(fā)器（完全集成的OC - 12接口器件）） |
| 文件頁(yè)數(shù)： | 9/29頁(yè) |
| 文件大?。?/td> | 1467K |
| 代理商： | S3038 |
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9
S3038
SONET/SDH/ATM OC-12 QUAD TRANSCEIVER
May 31, 2001 / Revision C
Figure 7. PIN Data Clocking with PICLK
Figure 8. REFCLK Forward PIN Clocking
REFCLK
S3038
PICLKx
PINx[7:0]
REF
OSCILLATOR
MAC
ASIC
PCLK
PLL
REFCLK
S3038
PICLKx
PINx[7:0]
REF
OSCILLATOR
MAC
ASIC
PCLK
PLL
The following figures illustrate the broad range of
transmit data clocking options supported by the
S3038.
Figure 7 demonstrates the flexibility afforded by the
S3038. A low jitter reference is provided directly to
the S3038 at either 1/8 or 1/16 the serial data rate.
This ensures minimum jitter in the synthesized clock
used for serial data transmission. A system clock
output at the 32-bit parallel rate, PCLK, is derived
from the PLL and provided to the upstream circuit as
a system clock. This clock can be buffered as re-
quired without concern about added delay. There is
no phase requirement placed upon PCLK and the
PICLKx clock, which is provided back to the S3038,
other than that they remain within
±
3 ns of the phase
relationship established at reset.
The S3038 also supports the traditional REFCLK
clocking and is illustrated in Figure 8. This approach
imposes significant challenges in maintaining timing
margins on the designer.
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