參數(shù)資料
型號(hào)： S3038
廠商： Applied Micro Circuits Corp.
英文描述： SONET/SDH/ATM OC-12 Quad Transceiver(SONET/SDH四收發(fā)器（完全集成OC-12接口器件）)
中文描述： 的SONET / SDH / ATM的的OC - 12四路收發(fā)器（SONET / SDH的四收發(fā)器（完全集成的OC - 12接口器件））
文件頁(yè)數(shù)： 10/29頁(yè)
文件大?。?/td> 1467K
代理商： S3038
10
S3038
SONET/SDH/ATM OC-12 QUAD TRANSCEIVER
May 31, 2001 / Revision C
The phase relationship between the edge transitions
of the data and those of the generated clock are
compared by a phase/frequency discriminator. Out-
put pulses from the discriminator indicate the
required direction of phase corrections. These
pulses are smoothed by an integral loop filter. The
output of the loop filter controls the frequency of the
Voltage Controlled Oscillator (VCO), which gener-
ates the recovered clock.
Frequency stability without incoming data is guaran-
teed by an alternate reference input (REFCLK) that
the PLL locks onto when data is lost. If the frequency
of the incoming signal varies by greater than the
value stated in Table 11 with respect to REFCLK,
the PLL will be declared out of lock, and the PLL will
lock to the reference clock. The assertion of LOS will
also cause an out of lock condition.
The loop filter transfer function is optimized to en-
able the PLL to track the jitter, yet tolerate the
minimum transition density expected in a received
SONET data signal.
The total loop dynamics of the clock recovery PLL
yield a jitter tolerance which exceeds the minimum
tolerance proposed for SONET equipment by the
Bellcore TA-NWT-000253 standard, shown in Figure 9.
Figure 9. Clock Recovery Jitter Tolerance
25k 65k
250k 5M
6.5k
300
Jitter Frequency (Hz)
30
0.15
1.5
15
Jitter
Amplitude
(Ul p-p)
Minimum proposed
tolerance
(TA-NWT-000253)
OC-12
Clock Recovery
Clock recovery generates a clock that is at the same
frequency as the incoming data bit rate at the RSD
input or, in loopback, the transmitter data output. The
clock is phase aligned by a Phase Locked Loop
(PLL) so that it samples the data in the center of the
data eye pattern.
RECEIVER OPERATION
The S3038 quad transceiver chip provides the first
stage of digital processing of a receive SONET STS-
12 bit-serial stream. It converts the bit-serial 622.08
Mbps data stream into a 77.76 Mbyte/sec 8-bit paral-
lel data format.
Data Input
Two differential receivers are provided for each
channel of the S3038. This supports switching be-
tween redundant switch fabrics for SONET
applications. A select signal RSDSEL is provided for
each channel to control the selection of primary or
secondary inputs. In addition, each channel supports
a diagnostic loopback mode in which the serial data
from the transmitter replaces external serial data.
The loopback functions for all four channels is con-
trolled by a single Diagnostic Loopback Enable
(DLEB) signal.
Clock recovery is performed on the incoming
scrambled NRZ data stream. A 77.76 MHz reference
clock is required for phase locked loop start-up and
proper operation under loss of signal conditions. An
integral prescaler and phase locked loop circuit is
used to multiply this reference to the nominal bit
rate.
A loopback mode is provided for diagnostic loopback
(transmitter to receiver).
相關(guān)PDF資料
PDF描述
S3040A SONET/SDH Clock Recovery Unit(帶片上高頻鎖相環(huán)的SONET/SDH時(shí)鐘恢復(fù)單元)
S3040B SONET/SDH Clock Recovery Unit(帶片上高頻鎖相環(huán)的SONET/SDH時(shí)鐘恢復(fù)單元)
S3040 OC-48 Clock Recovery Unit(OC-48時(shí)鐘恢復(fù)單元)
S3041 SONET/SDH/ATM OC-48 8:1 Transmitter(帶片上高頻鎖相環(huán)的8選1 SONET/SDH傳送器（集成SONET OC-48接口器件）)
S3042 SONET/SDH/ATM OC-48 1：8 Receiver(帶片上高頻鎖相環(huán)的1：8 SONET/SDH接收器（集成SONET OC-48接口器件）)
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