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參數資料
| 型號： | S3038 |
| 廠商： | Applied Micro Circuits Corp. |
| 英文描述： | SONET/SDH/ATM OC-12 Quad Transceiver(SONET/SDH四收發(fā)器（完全集成OC-12接口器件）) |
| 中文描述： | 的SONET / SDH / ATM的的OC - 12四路收發(fā)器（SONET / SDH的四收發(fā)器（完全集成的OC - 12接口器件）） |
| 文件頁數： | 11/29頁 |
| 文件大?。?/td> | 1467K |
| 代理商： | S3038 |
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11
S3038
SONET/SDH/ATM OC-12 QUAD TRANSCEIVER
May 31, 2001 / Revision C
Frame and Byte Boundary Detection
The frame and byte boundary detection circuitry
searches the incoming data for three consecutive A1
bytes followed immediately by three consecutive A2
bytes. Framing pattern detection is enabled and dis-
abled by the Out-Of-Frame (OOF) input. Detection is
enabled by a rising edge on OOF, and remains en-
abled for the duration that OOF is set High. It is
disabled when a framing pattern is detected and
OOF is no longer set High. When the framing pattern
detection is enabled, the framing pattern is used to
locate byte and frame boundaries in the incoming
data stream (RSD or looped transmitter data). The
timing generator block takes the located byte bound-
ary and uses it to block the incoming data stream
into bytes for output on the parallel output data bus
(POUT[7:0]). The frame boundary is reported on the
Frame Pulse (FP) output when any 48-bit pattern
matching the framing pattern is detected on the in-
coming data stream. When the framing pattern
detection is disabled, the byte boundary is frozen to
the location found when detection was previously
enabled. Only framing patterns aligned to the fixed
byte boundary are indicated on the FP output.
The probability that random data in an STS-12 stream
will generate the 48-bit framing pattern is extremely
small. It is highly improbable that a mimic pattern
would occur within one frame of data. Therefore, the
time to match the first frame pattern and to verify it
with down-stream circuitry, at the next occurrence of the
pattern, is expected to be less than the required 250
μ
s,
even for extremely high bit error rates.
Once down-stream overhead circuitry has verified
that frame and byte synchronization are correct, the
OOF input can be set low to disable the frame
search process from trying to synchronize to a mimic
frame pattern
Serial-to-Parallel Converter
The serial-to-parallel converter consists of three 8-bit
registers. The first is a serial-in, parallel-out shift reg-
ister, which performs serial to parallel conversion
clocked by the clock recovery block. The second is
an 8-bit internal holding register, which transfers
data from the serial to parallel register on byte
boundaries as determined by the frame and byte
boundary detection block. On the falling edge of the
free running POCLK, the data in the holding register
is transferred to an output holding register which
drives POUT[7:0].
The delay through the serial-to-parallel converter
can vary from 1.5 to 3.5 byte periods (12 to 28 serial
bit periods) measured from the first bit of an incom-
ing byte to the beginning of the parallel output of
that byte. The variation in the delay is dependent on
the alignment of the internal parallel load timing,
which is synchronized to the data byte boundaries,
with respect to the falling edge of POCLK, which is
independent of the byte boundaries. The advantage of
this serial to parallel converter is that POCLK is nei-
ther truncated nor extended during reframe
sequences.
OTHER OPERATING MODES
Diagnostic Loopback
When the Diagnostic Loopback Enable (DLEB) input is
active, a loopback from the transmitter to the re-
ceiver at the serial data rate can be set up for
diagnostic purposes. The differential serial output
data from the transmitter is routed to the serial-to-
parallel block in place of the normal data stream
(RSD).
Forward Clocking
For 77.76 MHz reference operation, the S3038 oper-
ates in the forward clocking mode. The PLL locks
the PCLK output of the transmitter section to the
REFCLK with a fixed and repeatable phase relation.
This allows the transmitter data source to also be
the timing source for the serial clock synthesis.
The rising edge of PCLK is locked to the rising edge
of REFCLK, with a maximum delay of 8 to 10 nsec
due to the PCLK TTL output driver.
Reset
The RESET signal initializes the internal counters, in
addition, the rising edge on OOF is required after
RESET to initialize the chip.
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相關代理商/技術參數 |
參數描述 |
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| S3038TB | 制造商:AppliedMicro 功能描述: |
| S30395-1-G | 制造商: 功能描述: 制造商:undefined 功能描述: |
| S30395-513G | 制造商: 功能描述: 制造商:undefined 功能描述: |
| S303AB | 制造商:Cinch Connectors 功能描述:Conn Wire to Board SKT 3 POS Solder Lug ST Panel Mount |
| S-303-AB | 功能描述:Jones 插頭和插槽 3C PNL MNT SOCKET RoHS:否 制造商:Molex 產品類型:Socket Connectors 系列:Beau 位置/觸點數量:8 電壓額定值:250 V 電流額定值:10 A 外殼材料:Thermoplastic 觸點材料:Phosphor Bronze 觸點電鍍:Tin-Lead |
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