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參數(shù)資料
| 型號： | S29XS064R0PBHW010 |
| 廠商： | SPANSION LLC |
| 元件分類： | PROM |
| 英文描述： | 4M X 16 FLASH 1.8V PROM, 80 ns, PBGA44 |
| 封裝： | 7.50 X 5 MM, LEAD FREE, FBGA-44 |
| 文件頁數(shù)： | 40/65頁 |
| 文件大?。?/td> | 2116K |
| 代理商： | S29XS064R0PBHW010 |
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July 22, 2011 S29VS_XS064R_00_06
S29VS/XS-R MirrorBit
Flash Family
45
Da ta
Sh e e t
(Adv a n ce
In f o r m ation)
14. Command is valid when device is ready to read array data or when device is in autoselect mode.
15. The total number of cycles in the command sequence is determined by the number of words written to the write buffer. The maximum
number of cycles in the command sequence is 37.
16. Command sequence resets device for next command after write-to-buffer operation.
17. Entry commands are needed to enter a specific mode to enable instructions only available within that mode.
18. The Exit command must be issued to reset the device into read mode. Otherwise the device will hang.
19. Requires the Reset command to configure the configuration register.
13. Write Operation Status
The device provides several bits to determine the status of a program or erase operation: DQ2, DQ3, DQ5,
DQ6, and DQ7. Table 13.2 on page 50 and the following subsections describe the function of these bits. DQ7
and DQ6 each offers a method for determining whether a program or erase operation is complete or in
progress.
13.1
DQ7: Data# Polling
The Data# Polling bit, DQ7, indicates to the host system whether an Embedded Program or Erase algorithm
is in progress or completed, or whether a bank is in Erase Suspend. Data# Polling is valid after the rising
edge of the final WE# pulse in the command sequence. Note that the Data# Polling is valid only for the
last word being programmed in the write-buffer-page during Write Buffer Programming. Reading
Data# Polling status on any word other than the last word to be programmed in the write-buffer-page
will return false status information.
During the Embedded Program algorithm, the device outputs on DQ7 the complement of the datum
programmed to DQ7. This DQ7 status also applies to programming during Erase Suspend. When the
Embedded Program algorithm is complete, the device outputs the datum programmed to DQ7. The system
must provide the program address to read valid status information on DQ7. If a program address falls within a
protected sector, Data# Polling on DQ7 is active for approximately tPSP, then that bank returns to the read
mode.
During the Embedded Erase algorithm, Data# Polling produces a “0” on DQ7. When the Embedded Erase
algorithm is complete, or if the bank enters the Erase Suspend mode, Data# Polling produces a “1” on DQ7.
The system must provide an address within any of the sectors selected for erasure to read valid status
information on DQ7.
After an erase command sequence is written, if all sectors selected for erasing are protected, Data# Polling
on DQ7 is active for approximately tASP, then the bank returns to the read mode. If not all selected sectors are
protected, the Embedded Erase algorithm erases the unprotected sectors, and ignores the selected sectors
that are protected. However, if the system reads DQ7 at an address within a protected sector, the status may
not be valid.
Just prior to the completion of an Embedded Program or Erase operation, DQ7 may change asynchronously
with DQ6–DQ0 while Output Enable (OE#) is asserted low. That is, the device may change from providing
status information to valid data on DQ7. Depending on when the system samples the DQ7 output, it may read
the status or valid data. Even if the device has completed the program or erase operation and DQ7 has valid
data, the data outputs on DQ6–DQ0 may be still invalid. Valid data on DQ7–DQ0 will appear on successive
read cycles.
Table 13.2 on page 50 shows the outputs for Data# Polling on DQ7. Figure 13.1 on page 46 shows the Data#
Polling algorithm. Figure 19.8 on page 60 in AC Characteristics shows the Data# Polling timing diagram.
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