參數(shù)資料
型號(hào)： S29XS064R0PBHW010
廠商： SPANSION LLC
元件分類： PROM
英文描述： 4M X 16 FLASH 1.8V PROM, 80 ns, PBGA44
封裝： 7.50 X 5 MM, LEAD FREE, FBGA-44
文件頁(yè)數(shù)： 10/65頁(yè)
文件大?。?/td> 2116K
代理商： S29XS064R0PBHW010
18
S29VS/XS-R MirrorBit
Flash Family
S29VS_XS064R_00_06 July 22, 2011
Data
Sheet
(Adv an ce
Inf o r m a t io n)
9.1
VersatileIO (VIO) Control
The VersatileIO (VIO) control allows the host system to set the voltage levels that the device generates at its
data outputs and the voltages tolerated at its data inputs to the same voltage level that is asserted on the
VCCQ pin.
9.2
Asynchronous Read
The device is in the Asynchronous mode when Bit 15 of the Configuration register is set to '1'. To read data
from the memory array, the system must first assert a valid address.
9.2.1
S29VS-R ADM Access
With CE# LOW, WE# HIGH, and OE# HIGH, the system presents the address to the device and sets AVD#
LOW. AVD# is kept LOW for at least tAVDP ns. The address is latched on the rising edge of AVD#.
9.2.2
S29XS-R AADM Access
With CE# LOW, WE# HIGH, and OE# HIGH, the system presents the upper address bits to DQ and sets
AVD# LOW. The system then sets OE# LOW. The upper address bits are set when AVD# goes HIGH.
The system then sets AVD# LOW again, with OE# HIGH to capture the lower address bits. The lower
address bits are latched on the next rising edge of AVD#.
Address access time (tACC) is equal to the delay from stable addresses to valid output data. The chip enable
access time (tCE) is the delay from stable CE# to valid data at the outputs. See AC Characteristics
9.3
Synchronous (Burst) Read Mode and Configuration Register
The device is capable of continuous sequential burst operation and linear burst operation of a preset length.
In order to use Synchronous (Burst) Read Mode the configuration register bit 15 must be set to 0.
Prior to entering burst mode, the system should determine how many wait states are needed for the initial
word of each burst access (see table below), what mode of burst operation is desired, how the RDY signal
transitions with valid data, and output drive strength. The system would then write the configuration register
command sequence. See Configuration Register on page 35 for further details.
When the appropriate number of Wait States have occurred, data is output after the rising edge of the CLK.
Subsequent words are output tBACC after the rising edge of each successive clock cycle, which automatically
increments the internal address counter. RDY indicates the initial latency and any subsequent waits.
9.3.1
S29VS-R ADM Access
To burst read data from the memory array in ADM mode, the system must assert CE# to VIL, and provide a
valid address while driving AVD# to VIL for one cycle. OE# must remain at VIH during the one cycle that AVD#
is low. The data appears on A/DQ15 -A/DQ0 when CE# remains Low, after OE# is Low and the synchronous
access times are satisfied. The next data in the burst sequence is read on each clock cycle that OE# and CE#
remain Low.
OE# does not terminate a burst access if it rises to VIH during a burst access. The outputs will go to high
impedance but the burst access will continue until terminated by CE# going to VIH, or AVD# returns to VIL
with a new address to initiate a another burst access.
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