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參數(shù)資料
| 型號： | S29XS064R0PBHW010 |
| 廠商： | SPANSION LLC |
| 元件分類： | PROM |
| 英文描述： | 4M X 16 FLASH 1.8V PROM, 80 ns, PBGA44 |
| 封裝： | 7.50 X 5 MM, LEAD FREE, FBGA-44 |
| 文件頁數(shù)： | 27/65頁 |
| 文件大?。?/td> | 2116K |
| 代理商： | S29XS064R0PBHW010 |
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July 22, 2011 S29VS_XS064R_00_06
S29VS/XS-R MirrorBit
Flash Family
33
Da ta
Sh e e t
(Adv a n ce
In f o r m ation)
11.3.2
Programmable Wait State Configuration
The programmable wait state feature informs the device of the number of clock cycles that must elapse after
AVD# is driven active before data will be available. This value is determined by the input frequency of the
device. Configuration Bit CR13–CR11 determine the setting (see Table 11.1).
The wait state command sequence instructs the device to set a particular number of clock cycles for the initial
access in burst mode. The number of wait states that should be programmed into the device is directly related
to the clock frequency.
Notes
1. Upon power-up or hardware reset, the default setting is seven wait states.
2. RDY will default to being active with data when the Wait State Setting is set to a total initial access cycle of 2.
It is recommended that the wait state command sequence be written, even if the default wait state value is
desired, to ensure the device is set as expected. A hardware reset will set the wait state to the default setting.
11.3.3
Programmable Wait State
The host system should set CR13-CR11 to 100 for a clock frequency of 66 MHz for the system/device to
execute at maximum speed.
Table 11.2 describes the typical number of clock cycles (wait states) for various conditions.
11.3.4
Handshaking
For optimal burst mode performance, the host system must set the appropriate number of wait states in the
flash device depending on the clock frequency.
The autoselect function allows the host system to determine whether the flash device is enabled for
handshaking.
Table 11.1 Programmable Wait State Settings
CR13
CR12
CR11
Total Initial Access Cycles
000
Reserved
001
3
010
4
011
5
100
6
1
0
1
7 (default)
110
8
111
9
Table 11.2 Wait States for Handshaking
Conditions at Address
Typical No. of Clock Cycles after AVD# Low
Clock Cycles
Frequency (Maximum MHz)
Initial address (VCCQ = 1.8 V)
666
780
895
9
108
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