參數(shù)資料
型號(hào)： S29XS064R0PBHW010
廠商： SPANSION LLC
元件分類： PROM
英文描述： 4M X 16 FLASH 1.8V PROM, 80 ns, PBGA44
封裝： 7.50 X 5 MM, LEAD FREE, FBGA-44
文件頁(yè)數(shù)： 26/65頁(yè)
文件大小： 2116K
代理商： S29XS064R0PBHW010
32
S29VS/XS-R MirrorBit
Flash Family
S29VS_XS064R_00_06 July 22, 2011
Data
Sheet
(Adv an ce
Inf o r m a t io n)
11. Command Definitions
Writing specific address and data commands or sequences into the command register initiates device
operations. Table 12.3 on page 43 defines the valid register command sequences. Writing incorrect
address and data values or writing them in the improper sequence resets the device to reading array data.
All addresses are latched on the rising edge of AVD#. All data is latched on the rising edge of WE#. Refer to
AC Characteristics on page 54 for timing diagrams.
11.1
Reading Array Data
The device is automatically set to reading array data after device power-up. No commands are required to
retrieve data in asynchronous mode. Each bank is ready to read array data after completing an Embedded
Program or Embedded Erase algorithm.
After the device accepts an Erase Suspend command, the corresponding bank enters the erase-suspend-
read mode, after which the system can read data from any non-erase-suspended sector. After completing a
programming operation in the Erase Suspend mode, the system may once again read array data with the
same exception. See 12.9, Erase Suspend/Erase Resume Commands on page 41 for more information.
After the device accepts a Program Suspend command, the corresponding bank enters the program-
suspend-read mode, after which the system can read data from any non-program-suspended sector within
the same bank.
The system must issue the reset command to return a bank to the read (or erase-suspend-read) mode if DQ5
goes high during an active program or erase operation, or if the bank is in the autoselect mode.
and Synchronous/Burst Read tables provide the read parameters, and Figure 19.3, on page 56 and Figure
19.4, on page 57 show the timings.
11.2
Set Configuration Register Command Sequence
The device uses a configuration register to set the various burst parameters: number of wait states, burst
read mode, RDY configuration, and synchronous mode active. The configuration register must be set before
the device will enter burst mode.
The configuration register is loaded with a four-cycle command sequence. The first two cycles are standard
unlock sequences. On the third cycle, the data should be D0h and address bits should be 555h. During the
fourth cycle, the configuration code should be entered onto the data bus with the address bus set to address
000h. Once the data has been programmed into the configuration register, a software reset command is
required to set the device into the correct state. The device will power up or after a hardware reset with the
default setting, which is in asynchronous mode. The register must be set before the device can enter
synchronous mode. The configuration register can not be changed during device operations (program, erase,
or sector lock).
11.3
Read Configuration Register Command Sequence
The configuration register can be read with a four-cycle command sequence. The first two cycles are
standard unlock sequences. On the third cycle, the data should be C6h and address bits should be 555h.
During the fourth cycle, the configuration code should be read out of the data bus with the address bus set to
address 000h. Once the data has been read from the configuration register, a software reset command is
required to set the device into the correct set mode.
11.3.1
Read Mode Setting
On power-up or hardware reset, the device is set to be in asynchronous read mode. This setting allows the
system to enable or disable burst mode during system operations.
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