參數(shù)資料
型號(hào): S29PL129N70GAIW03
廠商: Spansion Inc.
英文描述: 256/128/128 Mb (16/8/8 M x 16-Bit) CMOS, 3.0 Volt-only Simultaneous Read/Write, Page-Mode Flash Memory
中文描述: 256/128/128字節(jié)(16/8/8 M中的x 16位),3.0伏的CMOS只同步讀/寫(xiě),頁(yè)模式閃存
文件頁(yè)數(shù): 39/85頁(yè)
文件大小: 940K
代理商: S29PL129N70GAIW03
November 23, 2005 S29PL-N_00_A4
S29PL-N MirrorBit Flash Family
37
P r e l i m i n a r y
/* Example: Unlock Bypass Program Command */
/* Do while in Unlock Bypass Entry Mode! */
*((UINT16 *)bank_addr + 0x555) = 0x00A0; /* write program setup command */
*((UINT16 *)pa) = data; /* write data to be programmed */
/* Poll until done or error. */
/* If done and more to program, */
/* do above two cycles again. */
Table 7.17 Unlock Bypass Reset
/* Example: Unlock Bypass Exit Command */
*( (UINT16 *)base_addr + 0x000 ) = 0x0090;
*( (UINT16 *)base_addr + 0x000 ) = 0x0000;
7.4.9 W rite Operation Status
The device provides several bits to determine the status of a program or erase operation. The
following subsections describe the function of DQ1, DQ2, DQ3, DQ5, DQ6, and DQ7.
DQ7: Data# Polling.
The Data# Polling bit, DQ7, indicates to the host system whether an Em-
bedded Program or Erase algorithm is in progress or completed, or whether a bank is in Erase
Suspend. Data# Polling is valid after the rising edge of the final WE# pulse in the command se-
quence. Note that the Data# Polling is valid only for the last word being programmed in the write-
buffer-page during Write Buffer Programming. Reading Data# Polling status on any word other
than the last word to be programmed in the write-buffer-page returns false status information.
During the Embedded Program algorithm, the device outputs on DQ7 the complement of the
datum programmed to DQ7. This DQ7 status also applies to programming during Erase Suspend.
When the Embedded Program algorithm is complete, the device outputs the datum programmed
to DQ7. The system must provide the program address to read valid status information on DQ7.
If a program address falls within a protected sector, Data# polling on DQ7 is active for approxi-
mately t
PSP
, then that bank returns to the read mode.
During the Embedded Erase Algorithm, Data# polling produces a
0
on DQ7. When the Embedded
Erase algorithm is complete, or if the bank enters the Erase Suspend mode, Data# Polling pro-
duces a
1
on DQ7. The system must provide an address within any of the sectors selected for
erasure to read valid status information on DQ7.
After an erase command sequence is written, if all sectors selected for erasing are protected,
Data# Polling on DQ7 is active for approximately t
ASP
, then the bank returns to the read mode.
If not all selected sectors are protected, the Embedded Erase algorithm erases the unprotected
sectors, and ignores the selected sectors that are protected. However, if the system reads DQ7
at an address within a protected sector, the status may not be valid.
Just prior to the completion of an Embedded Program or Erase operation, DQ7 can change asyn-
chronously with DQ6 – DQ0 while Output Enable (OE#) is asserted low. That is, the device may
change from providing status information to valid data on DQ7. Depending on when the system
Table 7.16 Unlock Bypass Program
(LLD Function = lld_ UnlockBypassProgramCmd)
Cycle
Description
Operation
Word Address
Data
1
Program Setup Command
Write
Base + xxxh
00A0h
2
Program Command
Write
Program Address
Program Data
(LLD Function = lld_ UnlockBypassResetCmd)
Cycle
Description
Operation
Word Address
Data
1
Reset Cycle 1
Write
Base + xxxh
0090h
2
Reset Cycle 2
Write
Base + xxxh
0000h
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