參數(shù)資料
型號(hào)： S29NS128N0PBJW000
廠商： SPANSION LLC
元件分類(lèi)： DRAM
英文描述： Simultaneous Read/Write, Multiplexed, Burst Mode Flash Memory
中文描述： 8M X 16 FLASH 1.8V PROM, 80 ns, PBGA44
封裝： 9.20 X 8 MM, LEAD FREE, FBGA-44
文件頁(yè)數(shù)： 43/86頁(yè)
文件大?。?/td> 1036K
代理商： S29NS128N0PBJW000
S29NS-N_00_A12 June 13, 2006
S29NS-N MirrorBit Flash Family
41
D a t a
S h e e t
( A d v a n c e
I n f o r m a t i o n )
11.3.1
Unlock Bypass Command Sequence
The unlock bypass feature allows the system to program faster than the standard program command
sequence. The unlock bypass command sequence is initiated by first writing two unlock cycles. This is
followed by a third write cycle containing the unlock bypass command, 20h. That bank then enters the unlock
bypass mode.
During the unlock bypass mode only the command is valid. To exit the unlock bypass mode, the system must
issue the two-cycle unlock bypass reset command sequence. The first cycle must contain the bank address
and the data 90h. The second cycle need only contain the data 00h. The bank then returns to the read mode.
11.4
Program Command Sequence
11.4.1
Program Command Sequence
Programming is a four-bus-cycle operation. The program command sequence is initiated by writing two
unlock write cycles, followed by the program set-up command. The program address and data are written
next, which in turn initiate the Embedded Program algorithm. The system is
not
required to provide further
controls or timings. The device automatically provides internally generated program pulses and verifies the
programmed cell margin.
Table 11.4 on page 52
shows the address and data requirements for the program
command sequence.
When the Embedded Program algorithm is complete, that bank then returns to the read mode and addresses
are no longer latched. The system can determine the status of the program operation by monitoring DQ7 or
DQ6/DQ2. Refer to the
Write Operation Status
on page 55
for information on these status bits.
Any commands written to the device during the Embedded Program Algorithm are ignored.
Note that a
hardware reset
immediately terminates the program operation. The program command sequence should be
reinitiated once that bank has returned to the read mode, to ensure data integrity.
Programming is allowed in any sequence and across sector boundaries.
A bit cannot be programmed from
“0” back to a “1.”
Attempting to do so may causes that bank to set DQ5 = 1 (change-up condition). However,
a succeeding read will show that the data is still “0.” Only erase operations can convert a “0” to a “1.”
11.4.2
Program Command Sequence (Unlock Bypass Mode)
Once the device enters the unlock bypass mode, then a two-cycle unlock bypass program command
sequence is all that is required to program in this mode. The first cycle in this sequence contains the unlock
bypass program command, A0h; the second cycle contains the program address and data. Additional data is
programmed in the same manner. This mode dispenses with the initial two unlock cycles required in the
standard program command sequence, resulting in faster total programming time.
Table 11.4 on page 52
shows the requirements for the unlock bypass command sequences.
11.5
Accelerated Program
The device offers accelerated program operations through the ACC input. When the system asserts ACC on
this input, the device automatically enters the Unlock Bypass mode. The system may then write the two-cycle
Unlock Bypass program command sequence. The device uses the higher voltage on the ACC input to
accelerate the operation.
Figure 11.1
illustrates the algorithm for the program operation. Refer to
Table 19.5,
Erase/Program
Operations on page 69
and
Figure 19.6 on page 70
for timing diagrams.
相關(guān)PDF資料
PDF描述
S29NS128N0PBJW002 Simultaneous Read/Write, Multiplexed, Burst Mode Flash Memory
S29NS128N0PBJW003 Simultaneous Read/Write, Multiplexed, Burst Mode Flash Memory
S29NS128N0SBJW000 Simultaneous Read/Write, Multiplexed, Burst Mode Flash Memory
S29NS128N0SBJW002 Simultaneous Read/Write, Multiplexed, Burst Mode Flash Memory
S29NS128N0SBJW003 Simultaneous Read/Write, Multiplexed, Burst Mode Flash Memory
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
S29NS128N0PBJW002 制造商:SPANSION 制造商全稱(chēng):SPANSION 功能描述:Simultaneous Read/Write, Multiplexed, Burst Mode Flash Memory
S29NS128N0PBJW003 制造商:SPANSION 制造商全稱(chēng):SPANSION 功能描述:Simultaneous Read/Write, Multiplexed, Burst Mode Flash Memory
S29NS128N0SBJW000 制造商:SPANSION 制造商全稱(chēng):SPANSION 功能描述:Simultaneous Read/Write, Multiplexed, Burst Mode Flash Memory
S29NS128N0SBJW002 制造商:SPANSION 制造商全稱(chēng):SPANSION 功能描述:Simultaneous Read/Write, Multiplexed, Burst Mode Flash Memory
S29NS128N0SBJW003 制造商:SPANSION 制造商全稱(chēng):SPANSION 功能描述:Simultaneous Read/Write, Multiplexed, Burst Mode Flash Memory
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