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參數(shù)資料
| 型號： | S29NS128N0PBJW000 |
| 廠商： | SPANSION LLC |
| 元件分類： | DRAM |
| 英文描述： | Simultaneous Read/Write, Multiplexed, Burst Mode Flash Memory |
| 中文描述： | 8M X 16 FLASH 1.8V PROM, 80 ns, PBGA44 |
| 封裝： | 9.20 X 8 MM, LEAD FREE, FBGA-44 |
| 文件頁數(shù)： | 17/86頁 |
| 文件大小： | 1036K |
| 代理商： | S29NS128N0PBJW000 |
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S29NS-N_00_A12 June 13, 2006
S29NS-N MirrorBit Flash Family
15
D a t a
S h e e t
( A d v a n c e
I n f o r m a t i o n )
8.3
Requirements for Synchronous (Burst) Read Operation
The device is capable of seven different burst read modes: continuous burst read; 8-, 16-, and 32-word linear
burst reads with wrap around; and 8-, 16-, and 32-word linear burst reads without wrap around.
8.3.1
Continuous Burst
When the device first powers up, it is enabled for asynchronous read operation. The device is automatically
enabled for burst mode and addresses are latched on the first rising edge of CLK input, while AVD# is held
low for one clock cycle.
Prior to activating the clock signal, the system should determine how many wait states are desired for the
initial word (t
IACC
) of each burst session. The system would then write the Set Configuration Register
command sequence.
The initial word is output t
IACC
after the rising edge of the first CLK cycle. Subsequent words are output t
BACC
after the rising edge of each successive clock cycle, which automatically increments the internal address
counter.
Note that the device has a fixed internal address boundary that occurs every 128 words,
starting at address 00007Fh. The transition from the highest address 7FFFFFh to 000000h is also a
boundary crossing
. During a boundary crossing, there is a no additional latency between the valid read at
address 00007F and the valid read at address 000080 (or between addresses offset from these values by the
same multiple of 128 words) for frequencies equal to or lower than 66 Mhz. For frequencies higher than 66
Mhz, there is a latency of 1 cycle.
During the time the device is outputting data with the starting burst address not divisible by four, additional
waits are required. The RDY output indicates this condition to the system by deasserting.
Table 8.2
through
Table 8.5
shows the address latency as a function of variable wait states.
Table 8.2
Address Latency for 7, 6, and 5 Wait States
Word
0
7, 6, and 5 ws
D0
D1
D2
D3
D4
D5
D6
D7
D8
1
D1
D2
D3
1 ws
D4
D5
D6
D7
D8
2
D2
D3
1 ws
1 ws
D4
D5
D6
D7
D8
3
D3
1 ws
1 ws
1 ws
D4
D5
D6
D7
D8
Table 8.3
Address Latency for 4 Wait States
Word
0
4 ws
D0
D1
D2
D3
D4
D5
D6
D7
D8
1
D1
D2
D3
D4
D5
D6
D7
D8
D9
2
D2
D3
1 ws
D4
D5
D6
D7
D8
D9
3
D3
1 ws
1 ws
D4
D5
D6
D7
D8
D9
Table 8.4
Address Latency for 3 Wait States
Word
0
3 ws
D0
D1
D2
D3
D4
D5
D6
D7
D8
1
D1
D2
D3
D4
D5
D6
D7
D8
D9
2
D2
D3
D4
D5
D6
D7
D8
D9
D10
3
D3
1 ws
D4
D5
D6
D7
D8
D9
D10
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| S29NS128N0PBJW002 | Simultaneous Read/Write, Multiplexed, Burst Mode Flash Memory |
| S29NS128N0PBJW003 | Simultaneous Read/Write, Multiplexed, Burst Mode Flash Memory |
| S29NS128N0SBJW000 | Simultaneous Read/Write, Multiplexed, Burst Mode Flash Memory |
| S29NS128N0SBJW002 | Simultaneous Read/Write, Multiplexed, Burst Mode Flash Memory |
| S29NS128N0SBJW003 | Simultaneous Read/Write, Multiplexed, Burst Mode Flash Memory |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| S29NS128N0PBJW002 | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:Simultaneous Read/Write, Multiplexed, Burst Mode Flash Memory |
| S29NS128N0PBJW003 | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:Simultaneous Read/Write, Multiplexed, Burst Mode Flash Memory |
| S29NS128N0SBJW000 | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:Simultaneous Read/Write, Multiplexed, Burst Mode Flash Memory |
| S29NS128N0SBJW002 | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:Simultaneous Read/Write, Multiplexed, Burst Mode Flash Memory |
| S29NS128N0SBJW003 | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:Simultaneous Read/Write, Multiplexed, Burst Mode Flash Memory |
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