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參數(shù)資料
| 型號(hào)： | S29NS128N0PBJW000 |
| 廠商： | SPANSION LLC |
| 元件分類： | DRAM |
| 英文描述： | Simultaneous Read/Write, Multiplexed, Burst Mode Flash Memory |
| 中文描述： | 8M X 16 FLASH 1.8V PROM, 80 ns, PBGA44 |
| 封裝： | 9.20 X 8 MM, LEAD FREE, FBGA-44 |
| 文件頁數(shù)： | 27/86頁 |
| 文件大?。?/td> | 1036K |
| 代理商： | S29NS128N0PBJW000 |
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S29NS-N_00_A12 June 13, 2006
S29NS-N MirrorBit Flash Family
25
D a t a
S h e e t
( A d v a n c e
I n f o r m a t i o n )
8.24.1
Power-Up Write Inhibit
If WE# = CE# = RESET# = V
IL
and OE# = V
IH
during power up, the device does not accept commands on the
rising edge of WE#. The internal state machine is automatically reset to the read mode on power-up
8.25
Lock Register
The Lock Register consists of 3 bits. Each of these bits are non-volatile and read-only. DQ15-DQ3 are
reserved and are undefined.
Note
When the device lock register is programmed (PPB mode lock bit is programmed, password mode lock bit programmed, or the Secured
Silicon lock bit is programmed) all DYBs revert to the power-on default state.
8.26
Standby Mode
When the system is not reading or writing to the device, it can place the device in the standby mode. In this
mode, current consumption is greatly reduced, and the outputs are placed in the high impedance state,
independent of the OE# input.
The device enters the CMOS standby mode when the CE# and RESET# inputs are both held at V
CC
. The
device requires standard access time (t
CE
) for read access when the device is in either of these standby
modes, before it is ready to read data.
If the device is deselected during erasure or programming, the device draws active current until the operation
is completed.
I
CC3
in the
DC Characteristics
table represents the standby current specification.
8.27
Automatic Sleep Mode
The automatic sleep mode minimizes Flash device energy consumption. The device automatically enters this
mode when addresses and clock remain stable for t
ACC
+ 20 ns. The automatic sleep mode is independent of
the CE#, WE#, and OE# control signals. Standard address access timings provide new data when addresses
are changed. While in sleep mode, output data is latched and always available to the system. I
CC4
in the
DC
Characteristics
table represents the automatic sleep mode current specification.
8.28
RESET#: Hardware Reset Input
The RESET# input provides a hardware method of resetting the device to reading array data. When RESET#
is driven low for at least a period of t
RP
, the device immediately terminates any operation in progress, tristates
all outputs, and ignores all read/write commands for the duration of the RESET# pulse. The device also
resets the internal state machine to reading array data. The operation that was interrupted should be
reinitiated once the device is ready to accept another command sequence, to ensure data integrity.
Current is reduced for the duration of the RESET# pulse. When RESET# is held at V
SS
, the device draws
CMOS standby current (I
CC4
). If RESET# is held at V
IL
but not within V
SS
, the standby current will be greater.
RESET# may be tied to the system reset circuitry. A system reset would thus also reset the Flash memory,
enabling the system to read the boot-up firmware from the Flash memory.
Refer to the
AC Characteristics
tables for RESET# parameters and to
Figure 19.5 on page 68
for the timing
diagram.
8.28.1
V
CC
Power-up and Power-down Sequencing
The device imposes no restrictions on V
CC
power-up or power-down sequencing. Asserting RESET# to V
IL
is
required during the entire V
CC
power sequence until the respective supplies reach their operating voltages.
Once V
CC
attains its operating voltage, de-assertion of RESET# to V
IH
is permitted.
Table 8.11
Lock Register
DQ15-DQ3
DQ2
DQ1
DQ0
Undefined
Password Protection Mode Lock Bit
Persistent Protection Mode Lock Bit
Secured Silicon Sector
Protection Bit
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| S29NS128N0PBJW002 | Simultaneous Read/Write, Multiplexed, Burst Mode Flash Memory |
| S29NS128N0PBJW003 | Simultaneous Read/Write, Multiplexed, Burst Mode Flash Memory |
| S29NS128N0SBJW000 | Simultaneous Read/Write, Multiplexed, Burst Mode Flash Memory |
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相關(guān)代理商/技術(shù)參數(shù) |
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| S29NS128N0PBJW002 | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:Simultaneous Read/Write, Multiplexed, Burst Mode Flash Memory |
| S29NS128N0PBJW003 | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:Simultaneous Read/Write, Multiplexed, Burst Mode Flash Memory |
| S29NS128N0SBJW000 | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:Simultaneous Read/Write, Multiplexed, Burst Mode Flash Memory |
| S29NS128N0SBJW002 | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:Simultaneous Read/Write, Multiplexed, Burst Mode Flash Memory |
| S29NS128N0SBJW003 | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:Simultaneous Read/Write, Multiplexed, Burst Mode Flash Memory |
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