參數(shù)資料
型號(hào)： S29NS128N0PBJW000
廠商： SPANSION LLC
元件分類： DRAM
英文描述： Simultaneous Read/Write, Multiplexed, Burst Mode Flash Memory
中文描述： 8M X 16 FLASH 1.8V PROM, 80 ns, PBGA44
封裝： 9.20 X 8 MM, LEAD FREE, FBGA-44
文件頁(yè)數(shù)： 18/86頁(yè)
文件大小： 1036K
代理商： S29NS128N0PBJW000
16
S29NS-N MirrorBit Flash Family
S29NS-N_00_A12 June 13, 2006
D a t a
S h e e t
( A d v a n c e
I n f o r m a t i o n )
Table 8.6
through
Table 8.8
show the address/boundary crossing latency for variable wait state if a boundary
crossing occurs during initial access
The device will continue to output continuous, sequential burst data, wrapping around to address 000000h
after it reaches the highest addressable memory location, until the system asserts CE# high, RESET# low, or
AVD# low in conjunction with a new address. See
Table 8.1 on page 14
. The reset command does
not
terminate the burst read operation.
If the host system crosses a 128 word line boundary while reading in burst mode, and the device is not
programming or erasing, no additional latency will occur as described above. If the host system crosses the
bank boundary while the device is programming or erasing, the device will provide asynchronous read status
information. The clock will be ignored. After the host has completed status reads, or the device has completed
the program or erase operation, the host can restart a burst operation using a new address and AVD# pulse.
Table 8.5
Address Latency for 2 Wait States
Word
0
2 ws
D0
D1
D2
D3
D4
D5
D6
D7
D8
1
D1
D2
D3
D4
D5
D6
D7
D8
D9
2
D2
D3
D4
D5
D6
D7
D8
D9
D10
3
D3
D4
D5
D6
D7
D8
D9
D10
D11
Table 8.6
Address/Boundary Crossing Latency for 7, 6, and 5 Wait States
Word
0
7, 6, and 5 ws
D0
D1
D2
D3
1 ws
D4
D5
D6
D7
1
D1
D2
D3
1 ws
1 ws
D4
D5
D6
D7
2
D2
D3
1 ws
1 ws
1 ws
D4
D5
D6
D7
3
D3
1 ws
1 ws
1 ws
1 ws
D4
D5
D6
D7
Table 8.7
Address/Boundary Crossing Latency for 4 Wait States
Word
0
4 ws
D0
D1
D2
D3
D4
D5
D6
D7
D8
1
D1
D2
D3
1 ws
D4
D5
D6
D7
D8
2
D2
D3
1 ws
1 ws
D4
D5
D6
D7
D8
3
D3
1 ws
1 ws
1 ws
D4
D5
D6
D7
D8
Figure 8.1
Address/Boundary Crossing Latency for 3 Wait States
Word
0
3 ws
D0
D1
D2
D3
D4
D5
D6
D7
D8
1
D1
D2
D3
D4
D5
D6
D7
D8
D9
2
D2
D3
1 ws
D4
D5
D6
D7
D8
D9
3
D3
1 ws
1 ws
D4
D5
D6
D7
D8
D9
Table 8.8
Address/Boundary Crossing Latency for 2 Wait States
Word
0
2 ws
D0
D1
D2
D3
D4
D5
D6
D7
D8
1
D1
D2
D3
D4
D5
D6
D7
D8
D9
2
D2
D3
D4
D5
D6
D7
D8
D9
D10
3
D3
1 ws
D4
D5
D6
D7
D8
D9
D10
相關(guān)PDF資料
PDF描述
S29NS128N0PBJW002 Simultaneous Read/Write, Multiplexed, Burst Mode Flash Memory
S29NS128N0PBJW003 Simultaneous Read/Write, Multiplexed, Burst Mode Flash Memory
S29NS128N0SBJW000 Simultaneous Read/Write, Multiplexed, Burst Mode Flash Memory
S29NS128N0SBJW002 Simultaneous Read/Write, Multiplexed, Burst Mode Flash Memory
S29NS128N0SBJW003 Simultaneous Read/Write, Multiplexed, Burst Mode Flash Memory
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
S29NS128N0PBJW002 制造商:SPANSION 制造商全稱:SPANSION 功能描述:Simultaneous Read/Write, Multiplexed, Burst Mode Flash Memory
S29NS128N0PBJW003 制造商:SPANSION 制造商全稱:SPANSION 功能描述:Simultaneous Read/Write, Multiplexed, Burst Mode Flash Memory
S29NS128N0SBJW000 制造商:SPANSION 制造商全稱:SPANSION 功能描述:Simultaneous Read/Write, Multiplexed, Burst Mode Flash Memory
S29NS128N0SBJW002 制造商:SPANSION 制造商全稱:SPANSION 功能描述:Simultaneous Read/Write, Multiplexed, Burst Mode Flash Memory
S29NS128N0SBJW003 制造商:SPANSION 制造商全稱:SPANSION 功能描述:Simultaneous Read/Write, Multiplexed, Burst Mode Flash Memory
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