參數(shù)資料
型號： S29NS064N0SBJW003
廠商： SPANSION LLC
元件分類： DRAM
英文描述： Simultaneous Read/Write, Multiplexed, Burst Mode Flash Memory
中文描述： 4M X 16 FLASH 1.8V PROM, 80 ns, PBGA44
封裝： 7.70 X 6.20 MM, LEAD FREE, FBGA-44
文件頁數(shù)： 19/86頁
文件大小： 1036K
代理商： S29NS064N0SBJW003
S29NS-N_00_A12 June 13, 2006
S29NS-N MirrorBit Flash Family
17
D a t a
S h e e t
( A d v a n c e
I n f o r m a t i o n )
8.3.2
8-, 16-, and 32-Word Linear Burst with Wrap Around
These three modes are of the linear wrap around design, in which a fixed number of words are read from
consecutive addresses. In each of these modes, the burst addresses read are determined by the group within
which the starting address falls. The groups are sized according to the number of words read in a single burst
sequence for a given mode (see
Table 8.9
.)
As an example: if the starting address in the 8-word mode is 3Ah, and the burst sequence would be 3A-3B-
3C-3D-3E-3F-38-39h. The burst sequence begins with the starting address written to the device, but wraps
back to the first address in the selected group. In a similar fashion, the 16-word and 32-word Linear Wrap
modes begin their burst sequence on the starting address written to the device, and then wraps back to the
first address in the selected address group and terminates the burst read.
Note that in these three burst
read modes the address pointer does not cross the boundary that occurs every 128 words; thus, no
wait states are inserted (except during the initial access).
8.3.3
8-, 16-, and 32-Word Linear Burst without Wrap Around
In these modes, a fixed number of words (predefined as 8, 16, or 32 words) are read from consecutive
addresses starting with the initial word, which is written to the device. When the address is at the end of the
group address range (see Burst Address Groups Table), the burst read operation stops and the RDY output
goes low. There is no group limitation and is different from the Linear Burst with Wrap Around.
As an example, for 8-word length Burst Read, if the starting address written to the device is 3A, the burst
sequence would be 3A-3B-3C-3D-3E-3F-40-41h, and the read operation will be terminated after all eight
words. The 16-word and 32-word modes would operate in a similar fashion and continuously read to the
predefined 16 or 32 words accordingly.
Note: In this burst read mode, the address pointer may cross the
boundary that occurs every 128 words.
8.4
Programmable Wait State
The programmable wait state feature indicates to the device the number of additional clock cycles that must
elapse after AVD# is driven active before data will be available. Upon power up, the device defaults to the
maximum of seven total cycles. The total number of wait states is programmable from two to seven cycles.
For further details, see
Set Configuration Register Command Sequence
on page 37
.
8.5
Configuration Register
The device uses a configuration register to set the various burst parameters: number of wait states, burst
read mode, burst length, RDY configuration, and synchronous mode active.
8.6
Handshaking Feature
The handshaking feature allows the host system to simply monitor the RDY signal from the device to
determine when the initial word of burst data is ready to be read. The host system should use the
configuration register to set the number of wait states for optimal burst mode operation. The initial word of
burst data is indicated by the rising edge of RDY after OE# goes low.
Table 8.9
Burst Address Groups
Mode
Group Size
Group Address Ranges
8-word
8 words
0-7h, 8-Fh, 10-17h, 18-1Fh...
16-word
16 words
0-Fh, 10-1Fh, 20-2Fh, 30-3Fh...
32-word
32 words
00-1Fh, 20-3Fh, 40-5Fh, 60-7Fh...
相關(guān)PDF資料
PDF描述
S29NS128N0PBJW000 Simultaneous Read/Write, Multiplexed, Burst Mode Flash Memory
S29NS128N0PBJW002 Simultaneous Read/Write, Multiplexed, Burst Mode Flash Memory
S29NS128N0PBJW003 Simultaneous Read/Write, Multiplexed, Burst Mode Flash Memory
S29NS128N0SBJW000 Simultaneous Read/Write, Multiplexed, Burst Mode Flash Memory
S29NS128N0SBJW002 Simultaneous Read/Write, Multiplexed, Burst Mode Flash Memory
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