- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄365399 > S29NS064N0SBJW002 (SPANSION LLC) Simultaneous Read/Write, Multiplexed, Burst Mode Flash Memory PDF資料下載
參數(shù)資料
| 型號： | S29NS064N0SBJW002 |
| 廠商： | SPANSION LLC |
| 元件分類： | DRAM |
| 英文描述： | Simultaneous Read/Write, Multiplexed, Burst Mode Flash Memory |
| 中文描述： | 4M X 16 FLASH 1.8V PROM, 80 ns, PBGA44 |
| 封裝： | 7.70 X 6.20 MM, LEAD FREE, FBGA-44 |
| 文件頁數(shù)： | 16/86頁 |
| 文件大?。?/td> | 1036K |
| 代理商： | S29NS064N0SBJW002 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁當(dāng)前第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁
14
S29NS-N MirrorBit Flash Family
S29NS-N_00_A12 June 13, 2006
D a t a
S h e e t
( A d v a n c e
I n f o r m a t i o n )
8.
Device Bus Operations
This section describes the requirements and use of the device bus operations, which are initiated through the
internal command register. The command register itself does not occupy any addressable memory location.
The register is composed of latches that store the commands, along with the address and data information
needed to execute the command. The contents of the register serve as inputs to the internal state machine.
The state machine outputs dictate the function of the device.
Table 8.1
lists the device bus operations, the
inputs and control levels they require, and the resulting output. The following subsections describe each of
these operations in further detail.
Legend
L = Logic 0, H = Logic 1, X = Don’t Care.
Note
Terminating the current Burst cycle is determined by the falling edge of AVD#, while starting a new Burst read cycle is determined by the
rising edge of AVD#.
8.1
VersatileIO (V
IO
) Control
The VersatileIO (V
IO
) control allows the host system to set the voltage levels that the device generates at its
data outputs and the voltages tolerated at its data inputs to the same voltage level that is asserted on the
V
CCQ
pin.
8.2
Requirements for Asynchronous Read Operation (Non-Burst)
To read data from the memory array, the system must assert a valid address on A
max
–A16 and A/DQ15–A/
DQ0 while AVD# and CE# are at V
IL
. WE# should remain at V
IH
. Note that CLK must remain at V
IL
during
asynchronous read operations. The rising edge of AVD# latches the address, after which the system can
drive OE# to V
IL
. The data will appear on A/DQ15–A/DQ0. (See
Figure 19.4 on page 67
.) Since the memory
array is divided into banks, each bank remains enabled for read access until the command register contents
are altered.
Address access time (t
ACC
) is equal to the delay from stable addresses to valid output data. The chip enable
access time (t
CE
) is the delay from the stable addresses and stable CE# to valid data at the outputs. The
output enable access time (t
OE
) is the delay from the falling edge of OE# to valid data at the output.
The internal state machine is set for reading array data upon device power-up, or after a hardware reset. This
ensures that no spurious alteration of the memory content occurs during the power transition.
Table 8.1
Device Bus Operations
Operation
CE#
OE#
WE#
A
max
–16
Addr In
A/DQ15–0
RESET#
CLK
AVD#
Asynchronous Read
L
L
H
I/O
H
L
Write
L
H
L
Addr In
I/O
H
H/L
Standby (CE#)
H
X
X
X
HIGH Z
H
H/L
X
Hardware Reset
X
X
X
X
HIGH Z
L
X
X
Burst Read Operations
Load Starting Burst Address
L
H
H
Addr In
Addr In
H
Advance Burst to next address with appropriate
Data presented on the Data Bus
L
L
H
X
Burst
Data Out
H
H
Terminate current Burst read cycle
H
X
H
X
HIGH Z
H
X
Terminate current Burst read cycle via RESET#
X
X
H
X
HIGH Z
L
X
X
Terminate current Burst read cycle and start new
Burst read cycle
L
H
H
X
I/O
H
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| S29NS064N0SBJW003 | Simultaneous Read/Write, Multiplexed, Burst Mode Flash Memory |
| S29NS128N0PBJW000 | Simultaneous Read/Write, Multiplexed, Burst Mode Flash Memory |
| S29NS128N0PBJW002 | Simultaneous Read/Write, Multiplexed, Burst Mode Flash Memory |
| S29NS128N0PBJW003 | Simultaneous Read/Write, Multiplexed, Burst Mode Flash Memory |
| S29NS128N0SBJW000 | Simultaneous Read/Write, Multiplexed, Burst Mode Flash Memory |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| S29NS064N0SBJW003 | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:Simultaneous Read/Write, Multiplexed, Burst Mode Flash Memory |
| S29NS128J0LBAW00 | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:110 nm CMOS 1.8-Volt only Simultaneous Read/Write, Burst Mode Flash Memories |
| S29NS128J0LBAW000 | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:Burst Mode Flash Memories |
| S29NS128J0LBAW002 | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:Burst Mode Flash Memories |
| S29NS128J0LBAW003 | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:Burst Mode Flash Memories |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。