參數資料
型號： S29NS064N0SBJW000
廠商： SPANSION LLC
元件分類： DRAM
英文描述： Simultaneous Read/Write, Multiplexed, Burst Mode Flash Memory
中文描述： 4M X 16 FLASH 1.8V PROM, 80 ns, PBGA44
封裝： 7.70 X 6.20 MM, LEAD FREE, FBGA-44
文件頁數： 5/86頁
文件大小： 1036K
代理商： S29NS064N0SBJW000
S29NS-N_00_A12 June 13, 2006
S29NS-N MirrorBit Flash Family
3
D a t a
S h e e t
( A d v a n c e
I n f o r m a t i o n )
The host system can detect whether a program or erase operation is complete by using the device
status bit
DQ7 (Data# Polling) and DQ6/DQ2 (toggle bits). After a program or erase cycle has been completed, the
device automatically returns to reading array data.
The
sector erase architecture
allows memory sectors to be erased and reprogrammed without affecting the
data contents of other sectors. The devices are fully erased when shipped from the factory.
Hardware data protection
measures include a low V
CC
detector that automatically inhibits write operations
during power transitions. The devices also offer three types of data protection at the sector level.
Persistent
Sector Protection
provides in-system, command-enabled protection of any combination of sectors using a
single power supply at V
CC
.
Password Sector Protection
prevents unauthorized write and erase operations
in any combination of sectors through a user-defined 64-bit password. When at V
IL
,
WP#
locks the highest
two sectors. Finally, when ACC is at V
IL
, all sectors are locked.
The devices offer two power-saving features. When addresses have been stable for a specified amount of
time, the device enters the
automatic sleep mode
. The system can also place the device into the
standby
mode
. Power consumption is greatly reduced in both modes.
Device programming occurs by executing the program command sequence. This initiates the
Embedded
Program
algorithm - an internal algorithm that automatically times the program pulse widths and verifies
proper cell margin. The
Unlock Bypass
mode facilitates faster program times by requiring only two write
cycles to program data instead of four. Additionally,
Write Buffer Programming
is available on this family of
devices. This feature provides superior programming performance by grouping locations being programmed.
Device erasure occurs by executing the erase command sequence. This initiates the
Embedded Erase
algorithm - an internal algorithm that automatically preprograms the array (if it is not already fully
programmed) before executing the erase operation. During erase, the device automatically times the erase
pulse widths and verifies proper cell margin.
The
Program Suspend/Program Resume
feature enables the user to put program on hold to read data from
any sector that is not selected for programming. If a read is needed from the Persistent Protection area,
Dynamic Protection area, or the CFI area, after an program suspend, then the user must use the proper
command sequence to enter and exit this region. The program suspend/resume functionality is also available
when programming in erase suspend (1 level depth only).
The
Erase Suspend/Erase Resume
feature enables the user to put erase on hold to read data from, or
program data to, any sector that is not selected for erasure. True background erase can thus be achieved. If
a read is needed from the Persistent Protection area, Dynamic Protection area, or the CFI area, after an
erase suspend, then the user must use the proper command sequence to enter and exit this region.
The
hardware RESET# pin
terminates any operation in progress and resets the internal state machine to
reading array data. The RESET# pin may be tied to the system reset circuitry. A system reset would thus also
reset the device, enabling the system microprocessor to read boot-up firmware from the Flash memory
device.
The host system can detect whether a memory array program or erase operation is complete by using the
device status bit DQ7 (Data# Polling), DQ6/DQ2 (toggle bits), DQ5 (exceeded timing limit), DQ3 (sector erase
start timeout state indicator), and DQ1 (write to buffer abort). After a program or erase cycle has been
completed, the device automatically returns to reading array data.
The
sector erase architecture
allows memory sectors to be erased and reprogrammed without affecting the
data contents of other sectors.
The device is fully erased when shipped from the factory
.
Hardware data protection
measures include a low V
CC
detector that automatically inhibits write operations
during power transitions. The device also offers two types of data protection at the sector level. When at V
IL
,
WP#
locks the two outermost boot sectors at the top of memory.
When the ACC pin = V
IL
, the entire flash memory array is protected.
Spansion LLC Flash technology combines years of Flash memory manufacturing experience to produce the
highest levels of quality, reliability and cost effectiveness. The device electrically erases all bits within a
sector. The data is programmed using hot electron injection.
相關PDF資料
PDF描述
S29NS064N0SBJW002 Simultaneous Read/Write, Multiplexed, Burst Mode Flash Memory
S29NS064N0SBJW003 Simultaneous Read/Write, Multiplexed, Burst Mode Flash Memory
S29NS128N0PBJW000 Simultaneous Read/Write, Multiplexed, Burst Mode Flash Memory
S29NS128N0PBJW002 Simultaneous Read/Write, Multiplexed, Burst Mode Flash Memory
S29NS128N0PBJW003 Simultaneous Read/Write, Multiplexed, Burst Mode Flash Memory
相關代理商/技術參數
參數描述
S29NS064N0SBJW002 制造商:SPANSION 制造商全稱:SPANSION 功能描述:Simultaneous Read/Write, Multiplexed, Burst Mode Flash Memory
S29NS064N0SBJW003 制造商:SPANSION 制造商全稱:SPANSION 功能描述:Simultaneous Read/Write, Multiplexed, Burst Mode Flash Memory
S29NS128J0LBAW00 制造商:SPANSION 制造商全稱:SPANSION 功能描述:110 nm CMOS 1.8-Volt only Simultaneous Read/Write, Burst Mode Flash Memories
S29NS128J0LBAW000 制造商:SPANSION 制造商全稱:SPANSION 功能描述:Burst Mode Flash Memories
S29NS128J0LBAW002 制造商:SPANSION 制造商全稱:SPANSION 功能描述:Burst Mode Flash Memories
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