參數(shù)資料
型號(hào): S29NS064N0SBJW000
廠商: SPANSION LLC
元件分類(lèi): DRAM
英文描述: Simultaneous Read/Write, Multiplexed, Burst Mode Flash Memory
中文描述: 4M X 16 FLASH 1.8V PROM, 80 ns, PBGA44
封裝: 7.70 X 6.20 MM, LEAD FREE, FBGA-44
文件頁(yè)數(shù): 47/86頁(yè)
文件大?。?/td> 1036K
代理商: S29NS064N0SBJW000
S29NS-N_00_A12 June 13, 2006
S29NS-N MirrorBit Flash Family
45
D a t a
S h e e t
( A d v a n c e
I n f o r m a t i o n )
11.8
Sector Erase Command Sequence
11.8.1
Sector Erase Command Sequence
Sector erase in normal mode is a six bus cycle operation. The sector erase command sequence is initiated by
writing two unlock cycles, followed by a set-up command. Two additional unlock cycles are written, and are
then followed by the address of the sector to be erased, and the sector erase command.
Table 11.4 on page
52
shows the address and data requirements for the sector erase command sequence.
The device does
not
require the system to preprogram prior to erase. The Embedded Erase algorithm
automatically programs and verifies the entire memory for an all zero data pattern prior to electrical erase.
The system is not required to provide any controls or timings during these operations.
After the command sequence is written, a sector erase time-out of no less than t
SEA
, sector erase accept,
occurs. During the time-out period, additional sector addresses and sector erase commands may be written.
Loading the sector erase buffer may be done in any sequence, and the number of sectors may be from one
sector to all sectors. The time between these additional cycles must be less than t
SEA
. Any sector erase
address and command following the exceeded time-out may or may not be accepted.
Any command other
than Sector Erase or Erase Suspend during the time-out period resets that bank to the read mode.
The system can monitor DQ3 to determine if the sector erase timer has timed out (See the section on DQ3:
Sector Erase start timeout state indicator.). The time-out begins from the rising edge of the final WE# pulse in
the command sequence.
When the Embedded Erase algorithm is complete, the bank returns to reading array data and addresses are
no longer latched. Note that while the Embedded Erase operation is in progress, the system can read data
from the non-erasing banks. The system can determine the status of the erase operation by reading DQ7 or
DQ6/ DQ2 in the erasing bank. Refer to
Write Operation Status
on page 55
for information on these status
bits.
Once the sector erase operation has begun, only the Erase Suspend command is valid. All other commands
are ignored. However, note that a
hardware reset
immediately
terminates the erase operation. If that occurs,
the sector erase command sequence should be reinitiated once that bank has returned to reading array data,
to ensure data integrity.
11.8.2
Accelerated Sector Erase
The device offers accelerated sector erase operation through the ACC function. This method of erasing
sectors is faster than the standard sector erase command sequence.
The accelerated sector erase
function must not be used more than 100 times per sector.
In addition, accelerated sector erase should
be performed at room temperature (30
°
C +-10
°
C).
The following procedure is used to perform accelerated sector erase:
1. Sectors to be erased must be PPB and DYB cleared. All sectors that remain locked will not be
erased.
2. Apply 9V to the ACC input. This voltage must be applied at least 1 μs before executing step
3
3. Issue the standard chip erase command.
4. Monitor status bits DQ2/DQ6 or DQ7 to determine when erasure is complete, just as in the
standard erase operation. See
Write Operation Status
on page 55
for further details.
5. Lower ACC from 9V to V
CC
.
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