參數(shù)資料
型號: S29GL128N11FAIV10
廠商: SPANSION LLC
元件分類: DRAM
英文描述: 3.0 Volt-only Page Mode Flash Memory featuring 110 nm MirrorBit⑩ Process Technology
中文描述: 8M X 16 FLASH 3V PROM, 110 ns, PBGA64
封裝: 13 X 11 MM, FBGA-64
文件頁數(shù): 81/100頁
文件大小: 952K
代理商: S29GL128N11FAIV10
S29GL-N_00_B3 October 13, 2006
S29GL-N MirrorBit Flash Family
79
D a t a S h e e t
AC Characteristics
Hardware Reset (RESET#)
Notes:
1.
Not 100% tested. If ramp rate is equal to or faster than 1V/100μs with a falling edge of the RESET# pin initiated, the RESET# pin needs to
be held low only for 100μs for power-up.
Next generation devices may have different reset speeds. To increase system design considerations, please refer to the “Advance
Information on S29GL-P Hardware Reset (RESET#) and Power-up Sequence” section for advance reset speeds on S29GL-P devices.
2.
Parameter
Description
Speed
(Note 2)
Unit
JEDEC
Std.
t
Ready
RESET# Pin Low (During Embedded Algorithms)
to Read Mode
(Note 1)
Max
20
ns
t
Ready
RESET# Pin Low (NOT During Embedded
Algorithms) to Read Mode
(Note 1)
Max
500
ns
t
RP
RESET# Pulse Width
Min
500
ns
t
RH
Reset High Time Before Read
(Note 1)
Min
50
ns
t
RPD
RESET# Low to Standby Mode
Min
20
μs
t
RB
RY/BY# Recovery Time
Min
0
ns
RESET#
RY/BY#
RY/BY#
t
RP
t
Ready
Reset Timings NOT during Embedded Algorithms
t
Ready
CE#, OE#
t
RH
CE#, OE#
Reset Timings during Embedded Algorithms
RESET#
t
RP
t
RB
t
RH
Figure 13. Reset Timings
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