參數(shù)資料
型號(hào)： S29CD032G0RQFI012
廠商： SPANSION LLC
元件分類(lèi)： PROM
英文描述： 1M X 32 FLASH 2.7V PROM, 48 ns, PQFP80
封裝： LEAD FREE, PLASTIC, MO-108CB-1, QFP-80
文件頁(yè)數(shù)： 38/81頁(yè)
文件大小： 1276K
代理商： S29CD032G0RQFI012
March 3, 2009 S29CD-G_00_B1
S29CD-G Flash Family
41
Da ta
Shee t
(Prelim i nar y )
15.3
Read/Reset Command
After power-up or hardware reset, the device automatically enter the read state. It is not necessary to issue
the reset command after power-up or hardware reset. Standard microprocessor cycles retrieve array data,
however, after power-up, only asynchronous accesses are permitted since the Configuration Register is at its
reset state with burst accesses disabled.
The Reset command is executed when the user needs to exit any of the other user command sequences
(such as autoselect, program, chip erase, etc.) to return to reading array data. There is no latency between
executing the Reset command and reading array data.
The Reset command does not disable the Secured Silicon sector if it is enabled. This function is only
accomplished by issuing the Secured Silicon Sector Exit command.
15.4
Autoselect Command
Flash memories are intended for use in applications where the local CPU alters memory contents. As such,
manufacturer and device codes must be accessible while the device resides in the target system. PROM
programmers typically access the signature codes by raising A9 to VID. However, multiplexing high voltage
onto the address lines is not generally desired system design practice.
The device contains an Autoselect Command operation to supplement traditional PROM programming
methodology. The operation is initiated by writing the Autoselect command sequence into the command
register. The bank address (BA) is latched during the autoselect command sequence write operation to
distinguish which bank the Autoselect command references. Reading the other bank after the Autoselect
command is written results in reading array data from the other bank and the specified address. Following the
command write, a read cycle from address (BA)XX00h retrieves the manufacturer code of (BA)XX01h. Three
sequential read cycles at addresses (BA) XX01h, (BA) XX0Eh, and (BA) XX0Fh read the three-byte device ID
(The Autoselect Command requires the user to execute the Read/Reset command to return the device back
to reading the array contents.)
15.5
Program Command Sequence
Programming is a four-bus-cycle operation. The program command sequence is initiated by writing two
unlock write cycles, followed by the program set-up command. The program address and data are written
next, which in turn initiate the Embedded Program algorithm. The system is not required to provide further
controls or timings. The device automatically generates the program pulses and verifies the programmed cell
margin. Table 15.2 on page 52 and Table 15.3 on page 53 show the address and data requirements for the
program command sequence.
During the Embedded Program algorithm, the system can determine the status of the program operation by
using DQ7, DQ6, or RY/BY#. (See Write Operation Status on page 54 for information on these status bits.)
When the Embedded Program algorithm is complete, the device returns to reading array data and addresses
are no longer latched. Note that an address change is required to begin read valid array data.
Except for Program Suspend, any commands written to the device during the Embedded Program Algorithm
are ignored. Note that a hardware reset immediately terminates the programming operation. The command
sequence should be reinitiated once that bank returns to reading array data, to ensure data integrity.
Programming is allowed in any sequence and across sector boundaries. A bit cannot be programmed from
a 0 back to a 1. Attempting to do so may halt the operation and set DQ5 to 1, or cause the Data# Polling
algorithm to indicate the operation was successful. However, a succeeding read shows that the data is still 0.
Only erase operations can convert a 0 to a 1.
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