參數(shù)資料
型號： S29CD032G0RQFI012
廠商： SPANSION LLC
元件分類： PROM
英文描述： 1M X 32 FLASH 2.7V PROM, 48 ns, PQFP80
封裝： LEAD FREE, PLASTIC, MO-108CB-1, QFP-80
文件頁數(shù)： 19/81頁
文件大?。?/td> 1276K
代理商： S29CD032G0RQFI012
24
S29CD-G Flash Family
S29CD-G_00_B1 March 3, 2009
Data
Sheet
(Pre limin ar y)
12.4
Writing Commands/Command Sequences
To write a command or command sequence (which includes programming data to the device and erasing
sectors of memory), the system must drive WE# and CE# to VIL, and OE# to VIH.
The device features an Unlock Bypass mode to facilitate faster programming. Once the device enters the
Unlock Bypass mode, only two write cycles are required to program a word or byte, instead of four. See
Sector Erase and Program Suspend Command on page 45 for details on programming data to the device
using both standard and Unlock Bypass command sequences.
An erase operation can erase one sector, multiple sectors, or the entire device. Table 11.1 on page 18 to
Table 11.4 on page 21 indicate the address space that each sector occupies. A sector address consists of
the address bits required to uniquely select a sector. See Command Definitions on page 40 for details on
erasing a sector or the entire chip, or suspending/resuming the erase operation.
When in Synchronous read mode configuration, the device is able to perform both asynchronous and
synchronous write operations. CLK and ADV# address latch is supported in synchronous programming
mode. During a synchronous write operation, to write a command or command sequence, (which includes
programming data to the device and erasing sectors of memory), the system must drive ADV# and CE# to
VIL, and OE# to VIH when providing an address to the device, and drive WE# and CE# to VIL, and CE# to
VIH, when writing commands or data.
12.4.1
Accelerated Program and Erase Operations
The device offers accelerated program/erase operations through the ACC pin. When the system asserts VHH
(12V) on the ACC pin, the device automatically enters the Unlock Bypass mode. The system may then write
the two-cycle Unlock Bypass program command sequence to do accelerated programming. The device uses
the higher voltage on the ACC pin to accelerate the operation. A sector that is being protected with the WP#
pin is protected during accelerated program or Erase.
Note
The ACC pin must not be at VHH during any operation other than accelerated programming, or device damage can result.
12.4.2
Autoselect Functions
If the system writes the autoselect command sequence, the device enters the autoselect mode. The system
can then read autoselect codes from the internal register (which is separate from the memory array) on DQ7–
DQ0. Standard read cycle timings apply in this mode. See Autoselect Mode on page 25 and Autoselect
Command on page 41 for more information.
12.5
Automatic Sleep Mode (ASM)
The automatic sleep mode minimizes Flash device energy consumption. While in asynchronous mode, the
device automatically enables this mode when addresses remain stable for tACC + 60 ns. The automatic sleep
mode is independent of the CE#, WE# and OE# control signals. Standard address access timings provide
new data when addresses are changed. While in sleep mode, output data is latched and always available to
the system. While in synchronous mode, the device automatically enables this mode when either the first
active CLK level is greater than tACC or the CLK runs slower than 5 MHz. Note that a new burst operation is
required to provide new data.
ICC8 in DC Characteristics on page 60 represents the automatic sleep mode current specification.
相關PDF資料
PDF描述
S29CL032J0JFAM020 1M X 32 FLASH 3.3V PROM, 54 ns, PBGA80
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