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參數(shù)資料
| 型號： | S2102 |
| 廠商： | Applied Micro Circuits Corp. |
| 英文描述： | Dual Fibre Channel Device(光纖通道雙收發(fā)器) |
| 中文描述： | 雙光纖通道設(shè)備（光纖通道雙收發(fā)器） |
| 文件頁數(shù)： | 8/28頁 |
| 文件大小： | 294K |
| 代理商： | S2102 |
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8
DUAL FIBRE CHANNEL DEVICE
S2102
October 6, 2000 / Revision C
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Table 5. Output Clock Mode
Serial to Parallel Conversion
Once bit synchronization has been attained by the
S2102 CRU, the S2102 must synchronize to the 10
bit word boundary. Word synchronization in the
S2102 is accomplished by detecting and aligning to
the 8B/10B K28.5 codeword. The S2102 will detect
and byte-align to either polarity of the K28.5. Each
channel of the S2102 will detect and align to a K28.5
anywhere in the data stream. For TCLK ot REFCLK
mode operation, the presence of a K28.5 is indicated
for each channel by the assertion of the COM_DETx
signal.
Data Output
Data is output on the DOUT[0:9] outputs. The
COM_DETx signal is used to indicate the reception of
a valid K28.5 character.
The S2102 TTL outputs are optimized to drive 65
line impedances. Internal source matching provides
good performance on unterminated lines of reason-
able length.
Parallel Output Clock Rate
Two output clock modes are supported, as shown in
Table 5. When CMODE is High, a complementary
TTL clock at the data rate is provided on the RBC1/0x
outputs. Data should be clocked on the rising edge of
RBC1x. When CMODE is Low, a complementary TTL
clock at half the data rate is provided. Data should be
latched on the rising edge of RBC1x and the rising
edge of RBC0x.
In Fibre Channel applications, multiple consecutive
K28.5 characters cannot be generated. However, for
serial backplane applications this can occur. The
S2102 must be able to operate properly when mul-
tiple K28.5 characters are received. After the first
K28.5 is detected and aligned, the RBC1/0x clock
will operate without glitches or loss of cycles.
Receiver Output Clocking
The S2102 parallel output clock source is deter-
mined by the TMODE selection. When REFCLK
clocking is selected (TMODE = Low), the parallel
output clocks (RCxP/N) are sourced from the TCLKA
input. When TCLK clocking is selected (External
Clocking Mode), the parallel output clocks are de-
rived from the recovered clock from each channel.
Table 5A describes the receiver output clocking op-
tions available.
Table 5A. S2102 Data Clocking
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When TCLKA is the output clock source, REFCLK
and TCLKA must equal the parallel word rate
(CLKSEL = Low). Additionally, the recovered clocks
and the clock input on TCLKA must be frequency
locked in order to avoid overflow/underflow of the
internal FIFOs. The propagation delay between
TCLKA and DOUTx, listed in Table 21, shows that
the phase delay between TCLKA and the RCxP/N
outputs may vary more than a bit time based on
process variation.
The recommended clocking configuration for exter-
nal clocking mode (REFCLK input clocking) is shown
in Figure 7. TCLKA is sourced from TCLKO, which is
frequency locked to the Reference clock input.
REFCLK
TCLKO
SerDes
TCLKA
REF
OSCILLATOR
Controller/MAC
ASIC/FPGA
PLL
Parallel Data
RCxP/N
2
Recovered
Clock
Figure 7. External Receiver Clocking
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