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參數(shù)資料
| 型號： | S2102 |
| 廠商： | Applied Micro Circuits Corp. |
| 英文描述： | Dual Fibre Channel Device(光纖通道雙收發(fā)器) |
| 中文描述： | 雙光纖通道設備（光纖通道雙收發(fā)器） |
| 文件頁數(shù)： | 5/28頁 |
| 文件大?。?/td> | 294K |
| 代理商： | S2102 |
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5
S2102
DUAL FIBRE CHANNEL DEVICE
October 6, 2000 / Revision C
Figure 5. DIN Data Clocking with TBC
TRANSMITTER DESCRIPTION
The transmitter section of the S2102 contains a single
PLL which is used to generate the serial rate transmit
clock for all transmitters. Two channels are provided
with a variety of options regarding input clocking and
loopback. The transmitters operate at 1.062 GHz, 10
or 20 times the reference clock frequency.
Data Input
The S2102 has been designed to simplify the parallel
interface data transfer and provides the utmost in flex-
ibility regarding clocking of parallel data. The S2102
incorporates a unique FIFO structure on both the par-
allel inputs and the parallel outputs which enables the
user to provide a “clean” reference source for the PLL
and to accept a separate external clock which is used
exclusively to reliably clock data into the device. Data
can also be clocked in using the REFCLK.
Data is input to each channel of the S2102 nominally
as a 10 bit wide word. An input FIFO and a clock
input, TBCx, are provided for each channel of the
S2102. The device can operate in two different
modes. The S2102 can be configured to use either
the TCLKx (TCLK MODE) input or the REFCLK input
(REFCLK MODE). In TCLK or REFCLK mode, 10
bits of data are clocked into its FIFO with the TBCx
provided with each 10 bits. Table 1 provides a sum-
mary of the input modes of the S2102.
Operation in the TBC MODE makes it easier for us-
ers to meet the relatively narrow setup and hold time
window required by the 106.25 Mbps 10-bit inter-
face. The TBC signal is used to clock the data into
an internal holding register and the S2102 synchro-
nizes its internal data flow to ensure stable opera-
tion. However, regardless of the clock mode,
REFCLK is always the VCO reference clock. This
facilitates the provision of a clean reference clock
resulting in minimum jitter on the serial output. The
TBC must be frequency locked to REFCLK, but may
have an arbitrary phase relationship. Adjustment of
internal timing of the S2102 is performed during re-
set. Once synchronized, the user must ensure that
the timing of the TBC signal does not change by
more than
±
3 ns relative to the REFCLK.
Figure 5 demonstrates the flexibility afforded by the
S2102. A low jitter reference is provided directly to
the S2102 at either 1/10 or 1/20 the serial data rate.
This ensures minimum jitter in the synthesized clock
used for serial data transmission. A system clock
output at the parallel word rate, TCLKO, is derived
from the PLL and provided to the upstream circuit as
a system clock. The frequency of this output is con-
stant at the parallel word rate, 1/10 the serial data
Figure 6. FC DIN Clocking with REFCLK
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Table 1. Input Modes
REFCLK
S2102
106.25 MHz or 53.125 MHz
TBCx
DINx[0:9]
REF
OSCILLATOR
MAC
ASIC
TCLKO
PLL
REFCLK
S2102
TBCx
DINx[0:9]
REF
OSCILLATOR
MAC
ASIC
TCLKO
PLL
106.25 MHz
Note that internal synchronization of FIFOs is performed upon
de-assertion of RESET.
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